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Enhanced Voltage-Regulated Static Keeper Techniques For Reduced Standby Power

IP.com Disclosure Number: IPCOM000013511D
Original Publication Date: 1999-Oct-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 5 page(s) / 112K

Publishing Venue

IBM

Related People

Tony Correale: AUTHOR [+2]

Abstract

A Voltage Regulated Static Keeper (VRSK) technique, coupled with gated bypass devices is disclosed. The VRSK technique utilized in the manner described in “A Voltage-Regulated Static Keeper Technique For High-Performance ASICs”, Hiroshi Kanno et al, Proceedings of the 1998 (11th Annual) IEEE International ASIC Conference, pgs. 361-364, coupled with a gated bypass device can reduce operating power, while achieving low standby power. I. Introduction In the Kanno paper, the VRSK technique was proposed to create a static circuit that can achieve performance closer to that of dynamic logic. The resulting circuit produces speeds, power consumption, and noise immunity specs somewhere between that of static and dynamic logic implementations. This effectively gives the designer a static circuit, with higher speed, and lower switching power. One drawback to this circuit, is the standby power dissipation. The VRSK device limits the voltage at the internal node-Y(see figure-1) to VDD-|Vtp|, or GND+Vtn as described in the paper. This allows the down stream logic to leak. Given a high frequency without long wait or standby states, this is not a problem, as the switching power savings more than compensates for the increased standby power consumption. However, in today’s low power applications, sections of a design can be turned off, or put to sleep for an extended period of time. This allows an unused section of the chip to be free from needless clock switching, resulting in power savings. Under these circumstances, the higher standby power of the VRSK circuit would be at a clear disadvantage. Any power savings gained by the VRSK could be lost to higher standby current. This is particularly true for flip-flops which represent the vast majority of circuits employed in a typical design. Therefore, a means to reduce the standby current while preserving the power-performance attributes of the VRSK is desired.

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  Enhanced Voltage-Regulated Static Keeper Techniques For Reduced Standby Power

  A Voltage Regulated Static Keeper (VRSK) technique, coupled with gated bypass devices is disclosed. The VRSK technique utilized in the manner described in "A Voltage-Regulated Static Keeper Technique For High-Performance ASICs", Hiroshi Kanno et al, Proceedings of the 1998 (11th Annual) IEEE International ASIC Conference, pgs. 361-364, coupled with a gated bypass device can reduce operating power, while achieving low standby power.

I. Introduction

In the Kanno paper, the VRSK technique was proposed to create a static circuit that can achieve performance closer to that of dynamic logic. The resulting circuit produces speeds, power consumption, and noise immunity specs somewhere between that of static and dynamic logic implementations. This effectively gives the designer a static circuit, with higher speed, and lower switching power.

One drawback to this circuit, is the standby power dissipation. The VRSK device limits the voltage at the internal node-Y(see figure-1) to VDD-|Vtp|, or GND+Vtn as described in the paper. This allows the down stream logic to leak. Given a high frequency without long wait or standby states, this is not a problem, as the switching power savings more than compensates for the increased standby power consumption. However, in today's low power applications, sections of a design can be turned off, or put to sleep for an extended period of time. This allows an unused section of the chip to be free from needless clock switching, resulting in power savings. Under these circumstances, the higher standby power of the VRSK circuit would be at a clear disadvantage. Any power savings gained by the VRSK could be lost to higher standby current. This is particularly true for flip-flops which represent the vast majority of circuits employed in a typical design. Therefore, a means to reduce the standby current while preserving the power-performance attributes of the VRSK is desired.

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Vdd

Figure 1: Latch using VRSK

II. VRSK Bypass Device

The standby power originates from the fact that the circuit's internal node, Y, can drift over time from the full power supply potential to a potential of Vdd-|Vtp| or Gnd+Vtn thereby allowing circuitry connected to node-Y to leak. To eliminate the standby power consumption of the VRSK device, a bypass device can be employed to pull the voltage at the drain of the VRSK device to the rail voltage. This will eliminate the leakage current caused by the threshold drop at node-Y. These bypass devices are only enabled during long periods of inactivity such as sleep or nap modes. Control signals are generally available which define when a sleep, doze or nap mode is entered. For other applications, such as flip-flops which employ clock gating techniques to reduce active power, the gating signals which are used to activate the flip-flop for a particular clock cycle can also be used as gating signals for the VR...