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Method for a hardware implementation of WEP

IP.com Disclosure Number: IPCOM000013534D
Publication Date: 2003-Jun-18
Document File: 3 page(s) / 276K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a hardware implementation of Wired Equivalent Privacy (WEP) protocol. Benefits include improved performance and improved security.

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This is the abbreviated version, containing approximately 57% of the total text.

Method for a hardware implementation of WEP

Disclosed is a method for a hardware implementation of Wired Equivalent Privacy (WEP) protocol. Benefits include improved performance and improved security.

Background

        � � � � � Wired Equivalent Privacy is addressed in wireless local area network (WLAN) standard 802.11i (draft) dated November 2002 by the Institute for Electrical and Electronics Engineers (IEEE).

General description

        � � � � � The disclosed method is hardware implementation of WEP protocol in the 802.11i standard. This hardware implementation uses an RC4 encryption algorithm that operates in a WEP environment to produce ciphertext from plaintext and plaintext from ciphertext. This hardware implementation provides data encryption and authentication using a single pass over the data, using a single key.

        � � � � �

Advantages

        � � � � � The disclosed method provides advantages, including:

•        � � � � Improved performance due to the use of a single WEP engine for the receive and transmit processes

•        � � � � Improved performance due to the use of buffers for I/O devices

•        � � � � Improved performance due to the hardware processing at 1 byte per cycle for authentication and encryption

•        � � � � Improved security due to compliance with the WEP (802.11i) standard

Detailed description

                � � � � � � � � � � � The disclosed method is a hardware implementation for authentication and encryption, which combine software advantages and flexibility with the powerful and acceleration of a hardware mechanism. The architecture is comprised of two hardware channels that transmit/receive and preprocess microcode.

        � � � � � Several tasks are performed by hardware, including:

•        � � � � As Master, read the ciphertext or plaintext bytes from the I/O device to be authenticated and encrypt/decrypt them.

•        � � � � Process the authentication with 32-byte widths per cycle.

•        � � � � Encrypt the plaintext bytes for transmission (TX) and decrypt the ciphertext bytes for reception (RX).

•        � � � � Indicate the end of processing.

•        � � � � Indicate the authentication result status.

        � � � � � Several tasks are performed by software, including:

•        � � � � Configure the register set.

•        � � � � Start the hardware machine.

•        � � � � Write the plaintext bytes to the WEP hardware machine.

•        � � � � Read the end of processing status.

•        � � � � Read the authentication result for receive mode.

        � � � � � The processing flow for transmission includes the following steps...