Browse Prior Art Database

HSTL clock integrity monitor

IP.com Disclosure Number: IPCOM000013559D
Original Publication Date: 2000-Aug-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Abstract

HSTL clock integrity monitor The problem to fix is, in a system generating HSTL clocks for a slave part, how to monitor the integrity of these clocks. As described on figure 1, a clock is generated by the VCXO. A clock buffer gives more power to feed several adapters, let’s take one module. It is used to feed an adapter and it’s internal logic. The adapter send back the clock (feed back clock),and is connected to the Up input of the integrity monitor.An other module of the clock buffer is connected to tha Down input of the integrity monitor.The positive, negative and equal zero output of the integrity monitor is connected to readeable I/O of a microcontroller of the reference card. CLOCK BUFFER

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HSTL clock integrity monitor

HSTL clock integrity monitor

The problem to fix is, in a system generating HSTL clocks for a slave part, how to monitor the integrity of these clocks.

    As described on figure 1, a clock is generated by the VCXO. A clock buffer gives more power to feed several adapters, let's take one module. It is used to feed an adapter and it's internal logic. The adapter send back the clock (feed back clock),and is connected to the Up input of the integrity monitor.An other module of the clock buffer is connected to tha Down input of the integrity monitor.The positive, negative and equal zero output of the integrity monitor is connected to readeable I/O of a microcontroller of the reference card.

CLOCK BUFFER

REFERENCE CARD

ADAPTER LOGIC

internal logic

VCXO

  MICRO CONTROLLER

I/O1

I/O2

I/O3

INTEGRITY MONITOR

Up p

Up n

=0Down n

>0Down p

<0

ADAPTER CARD

Feed back clock

1

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FIGURE 1 GENERAL SCHEMATIC

    On the figure 2 , the schematic of the integrity detector shows that the CLOCK to be MONITORED is connected to the input of a "up" counting of a binary counter . This COUNTER counts up to 3, the binary output of this counter is compared to a static 0 value named offset by a logic comparator. The other input of the counter is the down. As we can see, if any problem occurs on the integrity of the clock : for example glitches on the transmitted clock or glitches on the feed back clock , or miss...