Browse Prior Art Database

High speed module interface in a single companion clock environment

IP.com Disclosure Number: IPCOM000013562D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Abstract

Disclosed is a mechanism that allow an ATM layer module to sample correctly receive

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 74% of the total text.

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High speed module interface in a single companion clock environment

Disclosed is a mechanism that allow an ATM layer module to sample correctly receive

data sent by a framer module.

Utopia standard requires that the ATM layer provides both transmit and receive clocks to the framer. On the transmit side, transmit data are sent along with transmit clock that acts as a companion clock and allow correct data sampling at the framer side. On the receive side, receive data are sent without companion clock leading to problem of sampling in the ATM layer. Utopia bus is typically switching at 104 Mhz but in the current application, the bus is switching at 125 Mhz.

The mechanism proposes to create a receive clock path in the ATM layer and framer modules so that the delay variations are minimum (figure).

clock subsystem Y

system clock

CLK_MISS

Delay Z is built with additional circuitry :

- D'a adapter driver delay - B'a PCB delay - R'f framer receiver delay - T'f framer clock tree delay (one branch only) - D'f framer driver delay
- B'f PCB delay - R'a adapter receiver delay - T'a adapter clock tree delay

clock selection multiplex

CLK_X

CLK_X_ACTIVITY

CLK_Y_ACTIVITY

CLK_Y

clock distribution Yclock distribution X

CLK_MISS

CLK_Y

CLK_X

clock failure detection mechanism

hand- shake bus

clock failure detection mechanism

CLK_Y

CLK_X

clock subsystem X

1

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The receive clock phase shift is as close as possible to the transmit clock path. At the cost of two additional I/Os on...