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# SEAL algorithm implemented in hardware

IP.com Disclosure Number: IPCOM000013564D
Original Publication Date: 2001-Apr-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 4 page(s) / 100K

IBM

## Abstract

Disclosed here is a method for hardware implementation of SEAL cryptography algorithm. Table 1 shows original SEAL algorithm[1][2]. Array T use SRAM memory and it's address can be generated one clock before. WP and a,b,c,d update operations can run parallel to final round operations. Table 2 shows modified equations suitable for hardware implementation. In Figure 1, we give an example of data-path circuit of SEAL hardware engine. Peek performance of this hardware is: 256 32 [bit] Rate[Mbit/sec] Freq[MHz] (12 9*64)

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Page 1 of 4

SEAL algorithm implemented in hardware

Disclosed here is a method for hardware implementation of SEAL cryptography algorithm.

Table 1 shows original SEAL algorithm[1][2]. Array T use SRAM memory and it's address can be generated one clock before. WP and a,b,c,d update operations can run parallel to final round operations. Table 2 shows modified equations suitable for hardware implementation. In Figure 1, we give an example of data-path circuit of SEAL hardware engine.

Peek performance of this hardware is:

256 * 32 [bit] Rate[Mbit/sec] = -------------------- * Freq[MHz] (12 + 9*64)

Reference

[1] Philip Rogaway and Don Coppersmith

A software optimized encryption algorithm Original(SEAL1.0)

LectureNotes 809 p56-63

[2] Philip Rogaway and Don Coppersmith

A software optimized encryption algorithm Update(SEAL3.0)

http://www.cs.ucdavis.edu/~rogaway/papers/

Original algorithm

p=a&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[p/4]; p=a&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[p/4]; p=a&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[p/4]; p=a&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[p/4];

p= a &0x7fc; b=c; c=d; d=ROT9(a); a=b+T[p/4]^ROT9(a); q= a &0x7fc; b=c; c=d; d=ROT9(a); a=b^T[q/4]+ROT9(a); p=(p+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[p/4]^ROT9(a); q=(q+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[q/4]+ROT9(a);

p=(p+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[p/4]; q=(q+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[q/4]; p=(p+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[p/4]; q=(q+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[q/4]; WP n1=d; n2=b; n3=a; n4=c;

Round
Operatio
n

1

Page 2 of 4

Update *wp = b + S[4*i]; wp++;

*wp = c ^ S[4*i+1]; wp++;

*wp = d + S[4*i+2]; wp++;

*wp = a ^ S[4*i+3]; wp++;

if(i&1) {

a += n3;

b += n4;

c ^= n3;

d ^= n4;

} else {

a += n1;

b += n2;

c ^= n1;

d ^= n2;

}

if(i&1) {

a += n3;

c += n4;

} else {

a += n1;

c += n2;

}

Table 1, Original SEAL 1.0/3.0 algorithm

Pipelined algorithm for hardware

p=ta=a&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[ta];p=ta=a&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[ta];p=ta=a&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[ta];p=ta=a&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[ta];

p=ta= a &0x7fc; b=c; c=d; d=ROT9(a); a=b+T[ta]^ROT9(a); q=ta= a &0x7fc; b=c; c=d; d=ROT9(a); a=b^T[ta]+ROT9(a); p=ta=(p+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b+T[ta]^ROT9(a); q=ta=(q+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[ta]+ROT9(a);

p=ta=(p+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[ta]; q=ta=(q+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[ta]; p=ta=(p+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[ta]; q=ta=(q+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[ta];

WP n1=d; n2=b; n3=a; n4=c;Update p=ta=(p+a)&0x7fc; b=c; c=d; d=ROT9(a); a=b^T[ta]...