Browse Prior Art Database

Reliable DMA for large communication packets

IP.com Disclosure Number: IPCOM000013574D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Related People

Dr Gili Mendel: AUTHOR [+2]

Abstract

Disclosed is a method allowing the DMA of arbitrary large user buffers from a host PC to an adapter while providing error detection. A Windows NT device driver and adapter typically maintain a common memory area to exchange commands. This command area is segmented into fixed Control Block buffers, also called FIFO entries, which are of a fixed predetermined size. There is also a fixed memory staging area (also referred to as the adapter send pool), from which the adapter will DMA buffers and which is allocated and managed by the Windows NT Device Driver. Unfortunately, Windows NT has no facility to allow a protocol stack (or other user), to use buffers directly from the adapter send pool. This requires the Windows NT Device Driver to copy data from the protocol buffers to the adapter send pool before the adapter can DMA data. This extra copy wastes CPU cycles and increases the latency of the data. This disclosure eliminates the need for this copy by enumerating the physical addresses of the protocol stack's buffers (or any user application's data buffer) in each FIFO entry, allowing the adapter to DMA directly from the user's buffer. Figure 1 shows two separate Control Blocks representing two separate data transmissions. Figure 2 provides a more detailed description of the Control Header in each Control Block. Each page of user memory is enumerated as a Physical Descriptor (PD) in the FIFO entry. Control Header

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Reliable DMA for large communication packets

    Disclosed is a method allowing the DMA of arbitrary large user buffers from a host PC to an adapter while providing error detection.

    A Windows NT* device driver and adapter typically maintain a common memory area to exchange commands. This command area is segmented into fixed Control Block buffers, also called FIFO entries, which are of a fixed predetermined size.

    There is also a fixed memory staging area (also referred to as the adapter send pool), from which the adapter will DMA buffers and which is allocated and managed by the Windows NT Device Driver. Unfortunately, Windows NT has no facility to allow a protocol stack (or other user), to use buffers directly from the adapter send pool. This requires the Windows NT Device Driver to copy data from the protocol buffers to the adapter send pool before the adapter can DMA data. This extra copy wastes CPU cycles and increases the latency of the data. This disclosure eliminates the need for this copy by enumerating the physical addresses of the protocol stack's buffers (or any user application's data buffer) in each FIFO entry, allowing the adapter to DMA directly from the user's buffer. Figure 1 shows two separate Control Blocks representing two separate data transmissions. Figure 2 provides a more detailed description of the Control Header in each Control Block. Each page of user memory is enumerated as a Physical Descriptor (PD) in the FIFO entry.

Control Header

Immediate Data

Physical Descriptor Physical Descriptor Unused Unused Unused

Control Header

Immediate Data

Physical Descriptor Physical Descriptor Physical Descriptor Unused Unused Unused Unused

Fixed size Slot N = Packet n

Fixed size Slot N+1 = packet n +1

Figure 1. Two separate user requests in two FIFO entries

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Immediate Data Number of PhysicalLengthDescriptors Miscellaneous Controls Fields Continue Bit

Figure 2. Control Header details

    In Win...