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Method for efficient ram access from the service processor

IP.com Disclosure Number: IPCOM000013576D
Original Publication Date: 2001-Jan-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Abstract

Viewing the contents of embedded arrays from an external service processor can be achieved by a sequence of scanning the array address and array controls via a long system ring scan, then clocking the chip, and then scanning out the data read. Similarly embedded array contents may be altered by scanning the array address, the array controls, and the array data and then cycling the clocks. While this process seems simple, the reality is that often logic interdependencies prevent setting all of the array address, data, and control inputs at the same time across all possible combinations of address, data, and control inputs. There needs to be a one-to-one correspondence between each array input and a scanable latch. Yet, most often there are L1 (master only) latches bounding the array inputs for arrays that are clocked (updated) with the L2 (slave) phase of the clock. For this case where the arrays are clocked with the L2 phase of the clock, the problem of maintaining a one-to-one correspondence between the array inputs and latches is automatically provided by the L1 "bounding" latches. The catch with using the L1 latches for service processor

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Method for efficient ram access from the service processor

Viewing the contents of embedded arrays from an external service processor can be achieved by a sequence of scanning the array address and array controls via a long system ring scan, then clocking the chip, and then scanning out the data read. Similarly embedded array contents may be altered by scanning the array address, the array controls, and the array data and then cycling the clocks. While this process seems simple, the reality is that often logic interdependencies prevent setting all of the array address, data, and control inputs at the same time across all possible combinations of address, data, and control inputs. There needs to be a one-to-one correspondence between each array input and a scanable latch. Yet, most often there are L1 (master only) latches bounding the array inputs for arrays that are clocked (updated) with the L2 (slave) phase of the clock. For this case where the arrays are clocked with the L2 phase of the clock, the problem of maintaining a one-to-one correspondence between the array inputs and latches is automatically provided by the L1 "bounding" latches. The catch with using the L1 latches for service processor

access is that the L2 phase clock would necessarily have to occur before the L1 phase in order to maintain the L1 address, data, and control values setup by the system scan initialization. Were the L1 phase to occur prior to the L2 phase, then the values setup in the L1 phase would change to the values waiting to be loaded based on the combinatorial logic feeding the arrays. It turns out that the L1 phase clock does occur prior to the L2 phase; therefore, a separate L2 phase clock gate dedicated for the arrays is implemented to allow the updating of the arrays while not updating the L1 latches sourcing the arrays. This clock gate is refered to henceforth as the RAM_C2. Note that even if the L2 phase were to occur prior to the L1 phase, then the same array correpondence problem may exist for those arrays clocked on the L1 clock phase and fed by mid-cycle L2 latches (L2-star scanable latches). The L2 phase latches would change from the scan initialization values before the array access on a subse...