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Test and Diagnosis of Global System Clock Distribution Network Defects in a Scan-based VLSI Design

IP.com Disclosure Number: IPCOM000013604D
Original Publication Date: 2000-Nov-18
Included in the Prior Art Database: 2003-Jun-18
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Abstract

This invention disclosure addresses the problem of effectively testing these system clock distribution networks or trees and pinpointing logical fault locations within these networks. Specifically, the problem addressed is that of system clock distribution test and diagnosis in scan based designs supported by a structural test methodology. These type of problems are usually encountered early in the technology's life cycle and their diagnosability is critical in improving the process so it quickly achieves manufacturing yield levels. An inability to improve the technology and yield of the device can greatly impact a program or at least severely minimize the revenue that could be realized. Rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed for understanding and improving the process. Since these clock distribution networks span the entire chip utilizing multiple levels of metals, it is important to develop a technique to locate any manufacturing defects caused by marginal design practices in a quick and efficient way. Figures and Drawings

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  Test and Diagnosis of Global System Clock Distribution Network Defects in a Scan-based VLSI Design

    This invention disclosure addresses the problem of effectively testing these system clock distribution networks or trees and pinpointing logical fault locations within these networks.

    Specifically, the problem addressed is that of system clock distribution test and diagnosis in scan based designs supported by a structural test methodology.

These type of problems are usually encountered early in the technology's life cycle and their diagnosability is critical in improving the process so it quickly achieves manufacturing yield levels. An inability to improve the technology and yield of the device can greatly impact a program or at least severely minimize the revenue that could be realized. Rapid diagnosis to a location for Physical Failure Analysis (PFA) is needed for understanding and improving the process. Since these clock distribution networks span the entire chip utilizing multiple levels of metals, it is important to develop a technique to locate any manufacturing defects caused by marginal design practices in a quick and efficient way.

Figures and Drawings

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Clock_tree_diag_dis.prz

Background Information

Before describing the solution to the problem referenced above we shall give a short overview of the scan based design and test methodology. Specifically, we shall discuss the LSSD [Ref. 1-3] as practiced in most IBM chip and system designs, although many of the basic concepts apply to other variations of scan designs.

The LSSD methodology is a system design and a Design-for-Test (DFT) approach that incorporates several basic test concepts, i.e. scan design. In such a design most of the device's storage elements, such as latches or registers are concatenated in one or more scan chains and can be externally accessible via one or more serial inputs and outputs. Storage elements that are not in this category are usually memory or other special macros that are isolated and tested independently. Furthermore, this design methodology ensures that all logic feedback paths are gated by one or more of these storage elements, thereby simplifying a sequential design into subsets of combinational logic sections as shown in Fig. 1 and Fig. 2.

These basic design concepts in conjunction with the associated system and scan clocking sequences greatly simplify the test generation, testing, and diagnosability of very complex logic structures. Every latch can be used as a pseudo Primary Input (PI) and as a pseudo Primary Output (PO) in addition to the standard PIs and POs to enhance the stimulation and observability of the device being tested or diagnosed. LSSD latches are typically implemented in a L1/L2 configuration where the L1 or master latch has t...