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BIPOLAR LOCKOUT FROM APPLICATION OF DEVICE FINGERING AND STACK RE-ORDERING ON CLOCKED DOMINO

IP.com Disclosure Number: IPCOM000013637D
Original Publication Date: 2000-Feb-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Abstract

When using Domino dynamic circuits, the first Domino gate after a latch can experience system failure due to the leakage current associated with the parasitic bipolar device that results from using the Silicon-on-Insulator technology. It is harder to fix the case of the first Domino gate after a latch predischarging cannot be used because the latch output may remain high for a very long period of time, such that the predischarging never discharges the internal nodes in the nfet tree. Thus the bodies could potentially be charged high anyway even though predischarging was added to the gate. By splitting the nfet stacks in the nfet tree of the Domino gate as shown in the figure, the bipolar leakage current can be cut in half. The figure shows an example of a 2-way AND gate whose inputs are TOP and BOT, and which would normally be implemented with one nfet stack consisting of three nfets, two for the inputs and one for the evaluate device. The nfet tree has been split into two stacks composed of N0, N1, and PSN0 on the left, and another stack composed of N0A, N1A, and PSN0A on the right. The fix works as follows: Even if the bodies of N0 and N0A are charged high, only one of the nfet stacks can experience the bipolar leakage current. For example if TOP will remain low while BOT is going high, then N0 will experience a bipolar leakage current but N0A will not. Conversely, if TOP is going high and BOT will remain low, N0A can experience a bipolar leakage current but N0 will not. Thus instead of having a bipolar current based on 15u of transistor width, the circuit only experiences a bipolar current based on 7.5u of width. Since the bipolar leakage current is proportional to the total W, it has effectively been cut in half. Now only one of the nfet stacks may experience a bipolar leakage current while the other may experience charge sharing, which is not typically a severe problem in Silicon-on-Insulator technologies. Summarizing, the fix consists of splitting the nfet stacks of the circuit in half, then cross-coupling the inputs to the resulting two nfet stacks. The bipolar leakage current, under worst case input conditions, is cut in half. This solution applies only to the first Domino circuit after a latch . 1 2

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  BIPOLAR LOCKOUT FROM APPLICATION OF DEVICE FINGERING AND STACK RE-ORDERING ON CLOCKED DOMINO

   When using Domino dynamic circuits, the first Domino gate after a latch can experience system failure due to the leakage current associated with the parasitic bipolar device that results from using the Silicon-on-Insulator technology. It is harder to fix the case of the first Domino gate after a latch - predischarging cannot be used because the latch output may remain high for a very long period of time, such that the predischarging never discharges the internal nodes in the nfet tree. Thus the bodies could potentially be charged high anyway even though predischarging was added to the gate. By splitting the nfet stacks in the nfet tree of the Domino gate as shown in the figure, the bipolar leakage current can be cut in half. The figure shows an example of a 2-way AND gate whose inputs are TOP and BOT, and which would normally be implemented with one nfet stack consisting of three nfets, two for the inputs and one for the evaluate device. The nfet tree has been split into two stacks composed of N0, N1, and PSN0 on the left, and another stack composed of N0A, N1A, and PSN0A on the right. The fix works as follows: Even if the bodies of N0 and N0A are charged high, only one of the nfet stacks can experience the bipolar leakage current. For example if TOP will remain low while BOT is going high, then N0 will experience a bipolar leakage current but N0A will not. Conversely, if...