Browse Prior Art Database

Performance Monitor Reset and Enable

IP.com Disclosure Number: IPCOM000013664D
Original Publication Date: 2001-Jan-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 1 page(s) / 37K

Publishing Venue

IBM

Abstract

A method to simultaneously Reset and Enable a Performance Monitor within a processor is disclosed. Most modern processors include a Performance Monitor Unit (PMU) which monitors performance sensitive events within the processor and counts them in one or more Performance Monitor Counters (PMCs). Ideally the overhead of collecting, accumulating, and retrieving the event counts should be as low as possible. This invention addresses the overhead of initializing the counters to a known state (all zero in this case) and initiating counting in a single step. Within the PMU exists one or more Monitor Mode Control Registers (MMCRs) which control the operation of the PMU. Fields within the MMCRs typically indicate which events are counted, in which PMC, and under what conditions. This invention uses a single bit field within a MMCR to signal the PMU that all PMCs are to be initialized to zero. The bit can also be used to initiate counting. There are at least two ways to use this invention: 1. As a reset bit only. In this case the normal state of the bit is zero. The PMU monitors the bit and when, under software control, it changes from a zero to a one the PMU immediately sets all of the PMCs to zero and at the same time resets the control bit to zero. 2. As a reset and enable bit. In this case the PMU monitors the bit as before. When the bit changes from a one to a zero the PMU stops accumulating event counts in the PMCs. When the bit changes from a zero to a one, all PMCs are initialized to zero and then the PMU resumes accumulating event counts.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 1

Performance Monitor Reset and Enable

A method to simultaneously Reset and Enable a Performance Monitor within a processor is disclosed. Most modern processors include a Performance Monitor Unit (PMU) which monitors performance sensitive events within the processor and counts them in one or more Performance Monitor Counters (PMCs). Ideally the overhead of collecting, accumulating, and retrieving the event counts should be as low as possible. This invention addresses the overhead of initializing the counters to a known state (all zero in this case) and initiating counting in a single step.

Within the PMU exists one or more Monitor Mode Control Registers (MMCRs) which control the operation of the PMU. Fields within the MMCRs typically indicate which events are counted, in which PMC, and under what conditions. This invention uses a single bit field within a MMCR to signal the PMU that all PMCs are to be initialized to zero. The bit can also be used to initiate counting. There are at least two ways to use this invention:

1. As a reset bit only. In this case the normal state of the bit is zero. The PMU monitors the bit and when, under software control, it changes from a zero to a one the PMU immediately sets all of the PMCs to zero and at the same time resets the control bit to zero.

2. As a reset and enable bit. In this case the PMU monitors the bit as before. When the bit changes from a one to a zero the PMU stops accumulating event counts in the PMCs. When the bit c...