# Polarity and Magnitude Detection Circuit

Original Publication Date: 2000-Sep-01

Included in the Prior Art Database: 2003-Jun-18

## Publishing Venue

IBM

## Abstract

There exists the need in many VLSI applications to determine if the sum of three or more vectors is positive or negative. For example, in the fused, multiply-add architecture of the floating-point unit on the G4 microprocessor, the exponents of the operands in the equation A C B must be added in such a manner to facilitate the alignment of the B mantissa with the A C product. The addition is of the form Ea Ec Eb K (Equation 1; where Ex is the exponent of the X operand and K is a constant). Given the aggressive cycle times of microprocessors, it is necessary to begin the alignment of the B mantissa to the A C product before Equation 1 is completed. This pre-alignment must be validated or corrected if the result of Equation 1 indicates the pre-alignment was incorrect. In the example architecture, one case for correction is when the result is negative, another is when the result is greater than or equal to 256. Both of which cannot be determined until after the alignment has already begun. Hence, the need for a polarity and magnitude detection circuit to correct, if necessary, the pre-alignment. In traditional two vector adders one creates partial sums which account for a carry-in of +0d or +1d. In three or four vector addition, one can create partial sums which account for a carry-in of +0d, +1d, +2d, and +3d. Where the four-bit carry vectors will then be used as selects in a carry select multiplexor configuration. To illustrate, 1 1 1 1 100b; thus, the "throw" is two bit positions over. For a number of reasons, it was deemed advantageous to create partial sums and partial carries for two-bit groupings (analogous to breaking up a large vector adder into two-bit adders). Further, for performance, the circuits produce decoded values for the partial sums and partial carries for the two-bit groupings. For example, the decoded carry vector for a two-bit grouping could have for values (0001 +0d, 0010 +1d, 0100 +2d, or 1000 +3d). Using this approach to realize Equation 1, the inputs to the carry select multiplexors are 4-bit decoded sums and 4-bit decoded carries for two-bit groupings (except for the single-bit MSB). That is, for the 13-bit exponents in the PowerPC floating-point architecture, the partial sum for bit 0 (MSB) is ps_0<0:1>, for bits 1 to 2, ps_1to2<0:3>, and likewise for all 2-bit groupings up to bits 11 to 12, which is ps_11to12<0:3>. Analogously, the partial carry for bits 1 to 2 is pc_1to2<0:3>, for bits 3 to 4 is pc_3to4<0:3>, and likewise for all 2-bit groupings up to bits 11 to 12, which is pc_11to12<0:3>. (The architecture is defined such that there is no carry out of bit 0.)

**This text was extracted from a PDF file.**

**This is the abbreviated version, containing approximately 37% of the total text.**

__Page 1 of 3__**Polarity and Magnitude Detection Circuit**

There exists the need in many VLSI applications to determine if the sum of three or more vectors is positive or negative. For example, in the fused, multiply-add architecture of the floating-point unit on the G4 microprocessor, the exponents of the operands in the equation A * C + B must be added in such a manner to facilitate the alignment of the B mantissa with the A * C product. The addition is of the form Ea + Ec - Eb + K (Equation 1; where Ex is the exponent of the X operand and K is a constant). Given the aggressive cycle times of microprocessors, it is necessary to begin the alignment of the B mantissa to the A * C product before Equation 1 is completed. This pre-alignment must be validated or corrected if the result of Equation 1 indicates the pre-alignment was incorrect. In the example architecture, one case for correction is when the result is negative, another is when the result is greater than or equal to 256. Both of which cannot be determined until after the alignment has already begun. Hence, the need for a polarity and magnitude detection circuit to correct, if necessary, the pre-alignment.

In traditional two vector adders one creates partial sums which account for a carry-in of +0d or +1d. In three or four vector addition, one can create partial sums which account for a carry-in of +0d, +1d, +2d, and +3d. Where the four-bit carry vectors will then be used as selects in a carry select multiplexor configuration. To illustrate, 1 + 1 + 1 + 1 = 100b; thus, the "throw" is two bit positions over. For a number of reasons, it was deemed advantageous to create partial sums and partial carries for two-bit groupings (analogous to breaking up a large vector adder into two-bit adders). Further, for performance, the circuits produce decoded values for the partial sums and partial carries for the two-bit groupings. For example, the decoded carry vector for a two-bit grouping could have for values (0001 = +0d, 0010 = +1d, 0100 = +2d, or 1000 = +3d).

Using this approach to realize Equation 1, the inputs to the carry select multiplexors are 4-bit decoded sums and 4-bit decoded carries for two-bit groupings (except for the single-bit MSB). That is, for the 13-bit exponents in the PowerPC floating-point architecture, the partial sum for bit 0 (MSB) is ps_0<0:1>, for bits 1 to 2, ps_1to2<0:3>, and likewise for all 2-bit groupings up to bits 11 to 12, which is ps_11to12<0:3>. Analogously, the partial carry for bits 1 to 2 is pc_1to2<0:3>, for bits 3 to 4 is pc_3to4<0:3>, and likewise for all 2-bit groupings up to bits 11 to 12, which is pc_11to12<0:3>. (The architecture is defined such that there is no carry out of bit

0.)

It was determined reasonable for 13-bit addition to produce four possible sums (+0d, +1d, +2d, and +3d) for the five MSB positions in parallel with the eight LSB positions; and then use the carry vector coming out of bit position eight to select the correct result from the fou...