Browse Prior Art Database

Circuit technique for realizing a non-DC power dissipating compare circuit.

IP.com Disclosure Number: IPCOM000013680D
Original Publication Date: 1999-Oct-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 6 page(s) / 97K

Publishing Venue

IBM

Related People

Tony Correale: AUTHOR [+2]

Abstract

The following disclosure describes a circuit configuration for realizing a high fan-in logic circuit, such as a NOR that can be used in performing a compare function in a computer chip. Compares are generally performance critical operations and are done using either dynamic or static logic circuitry. The use of dynamic logic generally requires a pre-charge clock or gating signal to precondition the circuit. Activation of the pre-charge clock is done prior to the arrival of the signals to be compared and thus requires a setup time. The signals to be compared must be stable prior to the deactivation of the pre-charge clock. If these conditions can be satisfied and there exists a pre-charge clock, the use of dynamic (pre-charged) logic to implement the compare function generally results in the smallest area and most performance optimized solution. The static implementations don’t have the need for a pre-charge clock, or have any leakage current problems or coupling concerns that are associated with dynamic nodes, but are generally physically larger and slower than the dynamic realizations. Within the realm of static circuits, there are two types; static power (DC) dissipating and non-DC power dissipating. The DC power dissipating configurations are generally smaller physically, but dissipate considerably higher power. The non-DC power dissipating static configurations are generally standard CMOS configurations with complementary p n-channel devices. This disclosure highlights an approach which employs the best attributes of the dc power dissipating implementation without it’s dc power dissipation. Figure 1 illustrates a basic compare function. It is comprised of n-bits of XOR2 gates feeding an n-way OR function. For the purposes of this discussion, one of the n-bit busses will be termed the A-bus while the other is referred to as the B-Bus. If any A-Bus bit miscompares relative to its’ B-Bus counterpart, then the output of the corresponding XOR will be a “1” , and the OR function will be a “1” , indicating a miscompare. When all the A-Bus bits match the B-Bus bits exactly then the outputs of all XORs are “0” and the OR function is a “0”, indicating a compare. The XOR function can be implemented by numerous means which is not the subject of this disclosure. It is the ‘wide’ OR function that is generally of interest from an area and performance perspective. The OR function can be implemented as a two level logic realization comprised of an n-way NOR followed by an inverter, or by multiple parallel n-input NOR gates feeding an m-way NAND gate. A0 B0 A1 B1 An Bn

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Page 1 of 6

Circuit technique for realizing a non-DC power dissipating compare circuit.

  The following disclosure describes a circuit configuration for realizing a high fan-in logic circuit, such as a NOR that can be used in performing a compare function in a computer chip.

Compares are generally performance critical operations and are done using either dynamic or static logic circuitry. The use of dynamic logic generally requires a pre-charge clock or gating signal to precondition the circuit. Activation of the pre-charge clock is done prior to the arrival of the signals to be compared and thus requires a setup time. The signals to be compared must be stable prior to the deactivation of the pre-charge clock. If these conditions can be satisfied and there exists a pre-charge clock, the use of dynamic (pre-charged) logic to implement the compare function generally results in the smallest area and most performance optimized solution. The static implementations don't have the need for a pre-charge clock, or have any leakage current problems or coupling concerns that are associated with dynamic nodes, but are generally physically larger and slower than the dynamic realizations. Within the realm of static circuits, there are two types; static power (DC) dissipating and non-DC power dissipating. The DC power dissipating configurations are generally smaller physically, but dissipate considerably higher power. The non-DC power dissipating static configurations are generally standard CMOS configurations with complementary p & n-channel devices. This disclosure highlights an approach which employs the best attributes of the dc power dissipating implementation without it's dc power dissipation.

Figure 1 illustrates a basic compare function. It is comprised of n-bits of XOR2 gates feeding an n-way OR function. For the purposes of this discussion, one of the n-bit busses will be termed the A-bus while the other is referred to as the B-Bus. If any A-Bus bit miscompares relative to its' B-Bus counterpart, then the output of the corresponding XOR will be a "1" , and the OR function will be a "1" , indicating a miscompare. When all the A-Bus bits match the B-Bus bits exactly then the outputs of all XORs are "0" and the OR function is a "0", indicating a compare. The XOR function can be implemented by numerous means which is not the subject of this disclosure. It is the 'wide' OR function that is generally of interest from an area and performance perspective. The OR function can be implemented as a two level logic realization comprised of an n-way NOR followed by an inverter, or by multiple parallel n-input NOR gates feeding an m-way NAND gate.

A0 B0 A1 B1 An Bn

...

XOR

XOR

XOR

X0 X1 Xn

N - Input OR

1 = Miscompare

Figure 1: Compare Logical Realization

1

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In the case of the dynamic realization of the comparator, the n-way NOR is usually implemented using nfet only transistors for the "pull-down" operation and a single gated / clocked pfet device for p...