Browse Prior Art Database

Real-Time Sampling Point Adjustment

IP.com Disclosure Number: IPCOM000013760D
Original Publication Date: 2001-Mar-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Abstract

High speed serial links generally have a very tight jitter budget. The eye closing at the receiver input is typically in the 75% range. The individual bit however has a considerably larger valid time. This may be verified by measuring a pseudo eye diagram with the trigger signal generated from the incoming data stream (in conventional eye diagrams the clock is used as trigger signal). In high speed serial links, the incoming data stream is oversampled in many cases in order to have several points for data detection and the phase synchronization control loop. The idea of real time sampling point adjustment is based on the above observations: The edges of the incoming data stream are used for a real time and adaptive shift of the sampling point towards its optimum. If no edge is detected, the previous sampling position or an medium setting may be used. Majority voting may further be used to enhance high speed jitter suppression. The concept of real time sampling point adjustment is demonstrated in the figure below. It is assumed, that a ring oscillator generates six sampling phases and a phase rotator is able to shift all six phases to any position. In each decision cycle, the two last samples from the previous cycle are used as additional information about the history of the incoming data stream. This way, a total of eight samples are used. Pipelined logic is used to generate an up/down signal for the phase rotator and to select the output data bit. It is the goal of the algorithm that processes the eight samples to center the edges on the first fife samples (read: at sample 3) and the data on the last six samples (read: on sample 6). In order to have information about the data edges and the data levels at the same time, the time interval used for analysis is approximately 140% of the data bit period. This large analysis interval is divided into two overlapping ranges: The first 2/3 are tested for the occurrence of a data edge and the last 3/4 are used for potential data sampling. The result of the edge test is used for the determination witch of the sampled data is used in the final selection.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Real-Time Sampling Point Adjustment

  High speed serial links generally have a very tight jitter
budget. The eye closing at the receiver input is typically in the
75% range. The individual bit however has a considerably larger
valid time. This may be verified by measuring a pseudo eye diagram
with the trigger signal generated from the incoming data stream (in
conventional eye diagrams the clock is used as trigger signal). In
high speed serial links, the incoming data stream is oversampled in
many cases in order to have several points for data detection and
the phase synchronization control loop.

The idea of real time sampling point adjustment is based on the
above observations: The edges of the incoming data stream are
used for a real time and adaptive shift of the sampling point
towards its optimum. If no edge is detected, the previous
sampling position or an medium setting may be used. Majority
voting may further be used to enhance high speed jitter
suppression.

The concept of real time sampling point adjustment is
demonstrated in the figure below. It is assumed, that a ring
oscillator generates six sampling phases and a phase rotator is
able to shift all six phases to any position. In each decision
cycle, the two last samples from the previous cycle are used as
additional information about the history of the incoming data
stream. This way, a total of eight samples are used. Pipelined
logic is used to generate an up/down signal for the phase rotator
and to select the output data bit....