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Bit Line Charge Up Circuit for Loadless Four-Transistor SRAM

IP.com Disclosure Number: IPCOM000013763D
Original Publication Date: 2002-Apr-11
Included in the Prior Art Database: 2003-Jun-18
Document File: 4 page(s) / 114K

Publishing Venue

IBM

Abstract

Bit-Line Charge Up Circuit for Loadless Four-Transistor SRAM.

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Bit Line Charge Up Circuit for Loadless Four-Transistor SRAM

Bit-Line Charge Up Circuit for Loadless Four-Transistor SRAM.

This paper describes circuit technique which reduces influence of coupling noise of adjacent bit-lines in loadless four transistor SRAM array. This circuit tequnique uses cross coupled pfet devices on a bit-line pair to recover voltage drop which occurred during a read access cycle. These added device size is small, and any additional control signal is not required. This technique is suitable for the loadless four transistor SRAM array using a direct sensing scheme or no sense amplifier scheme.

The loadless four-transistor SRAM cell does not have load devices which six-transistor SRAM cell usually has. The stored high voltage(=vdd voltage) in the four-transistor SRAM cell is kept by leak current which comes from bit-line through an access transistor. Therefore when the cell is accessed, this high level node is affected by coupling noise of adjacent bit-lines, and the voltage of the node is dropped from vdd voltage if there is no restoring devices on the bit-lines. This voltage drop becomes a cause of miss-read operation or having a retention time. Because the high voltage in a cell is kept by very small leak current only. Therefore this leak current can not recover the voltage drop within a cycle time.

Some schemes are known for reducing or improving the voltage drop. #1. use of twisted bit-line layout. #2. activating pre-charge devices during the read cycle, too. #3. use of a sense amplifier for restoring cell.

The #1 can reduce cross coupling noise, but can not get rid of it at all. Also complicated layout is required. The #2 can recover or remove the voltage drop, but a current through pass from the pre-charge device to cell's gnd wastes some power. The #3 can restore the cell data, but it needs to swing a bit-line pair rail to rail. This scheme is also consuming additional power.

Fig. 1 shows comparison of simulated bit-line waveforms of read cycle. The bit-lines are precharged to full Vdd during standby. The dashed line shows the bit-line voltage of when there is no circuit for recovering the voltage drop. In this case, the dropped voltage are read and are stored to the cell. When the next read access comes, then the voltage-droped-bit-line is affected again. In the result, the bit-line voltage is dropped furthermore and the stored voltage also becomes lower with every read access. This is a cause of miss-read or having a retention time in spite of SRAM.

The proposed circuit is show in Fig. 2. Two PFETs ,T1 and T2, are added on a bit-line-pair. Their source...