Browse Prior Art Database

Method to toggle a memory bus by indirect control in a memory application exerciser that can validate successful operation.

IP.com Disclosure Number: IPCOM000013770D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Abstract

Disclosed is a method that provides the ability to flip the data on a computer processor to memory bus within a program running on an operating system using indirect control. This method allows data to flip the processor/memory bus from one state to it's ones complement. In other words, on a 64 bit processor/memory bus to first write a pattern to that bus then flip the 1s to 0s and 0s to 1s for that same bus width. This allows memory application tests which generate the worse case switching transients on that bus. It proved to be a very good method to stress crosstalk between lines. Also, because of the ability to change the addressing of the buffer this has also proven useful to validate other buses within the memory hierarchy. The main requirement was to toggle the data bus from one state to it's opposite state. In other words, on a 64 bit processor/memory bus to first write a pattern to that bus then flip the 1s to 0s and 0s to 1s for that same bus width. This was relatively straightforward. To extend the flexibility and usefulness for a memory application exerciser to validate a wide variety of permutations the following other characteristics should be included. The width of the bus can be programmable in the method to allow testing of various size busses within any platform. For instance, to stress a processor/memory bus which is 64bits then this bus width of two DWORDs must selected if the data type used is DWORD. (1 Huge or 2 DWords or 4 Words or 8 Bytes). The data type selection would provide some timing flexibility because cache line write operations less than a cache line size would undergo read/modify write type operations. The address step selection allows the method the ability to toggle the bus in adjacent virtual addresses or further away. Also, by selecting the size of the buffer being tested different allows different areas within the memory hierarchy to be tested ranging from caches, physical memory or even disk. A combination of all these characteristics is shown below for write and read methods. Write Method. How many operations of this test object that you want to execute? DWORD dwNumberOfTransfers= 0xA00000;

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  Method to toggle a memory bus by indirect control in a memory application exerciser that can validate successful operation.

    Disclosed is a method that provides the ability to flip the data on a computer processor to memory bus within a program running on an operating system using indirect control. This method allows data to flip the processor/memory bus from one state to it's ones complement. In other words, on a 64 bit processor/memory bus to first write a pattern to that bus then flip the 1s to 0s and 0s to 1s for that same bus width. This allows memory application tests which generate the worse case switching transients on that bus. It proved to be a very good method to stress crosstalk between lines. Also, because of the ability to change the addressing of the buffer this has also proven useful to validate other buses within the memory hierarchy.

The main requirement was to toggle the data bus from one state to it's opposite state. In other words, on a 64 bit processor/memory bus to first write a pattern to that bus then flip the 1s to 0s and 0s to 1s for that same bus width. This was relatively straightforward.

To extend the flexibility and usefulness for a memory application exerciser to validate a wide variety of permutations the following other characteristics should be included. The width of the bus can be programmable in the method to allow testing of various size busses within any platform. For instance, to stress a processor/memory bus which is 64bits then this bus width of two DWORDs must selected if the data type used is DWORD. (1 Huge or 2 DWords or 4 Words or 8 Bytes). The data type selection would provide some timing flexibility because cache line write operations less than a cache line size would undergo read/modify write type operations. The address step selection allows the method the ability to toggle the bus in adjacent virtual addresses or further away. Also, by selecting the size of the buffer being tested different allows different areas within the memory hierarchy to be tested ranging from caches, physical memory or even disk. A combination of all these characteristics is shown below for write and read methods.

// Write Method. // How many operations of this test object that you want to execute? DWORD dwNumberOfTransfers= 0xA00000;

// What is the bus width of the data type? Phrased another way how many transfers of the type TNewType occur before you do a 1s complement.
// In this case assume the data type for TNewType is DWORD to aid in the example.

DWORD dwBusWidthInTypeSize = 2;

// Set the data that need to be loaded into the data type. This could be any number including a random number. TNewType m_tTempData = 0xFFFFFFFF;

// Pointer to current location in memory buffer. TNewType * m_tpByteAddress ;

// Buffer increment. m_dwAddressStepSize; // This could also be a random number.

// Initialize the pointer to the buffer to 4 data types away. This could be 4 DW, Words, Byte depending on TNewType. m_nAddress...