Browse Prior Art Database

Data integrity on parity-less buses

IP.com Disclosure Number: IPCOM000013773D
Original Publication Date: 2001-Mar-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 1 page(s) / 42K

Publishing Venue

IBM

Abstract

A number of processors do not implement parity on data buses. This can lead to errors in operation or corruption of data as errors during data transfer cannot be spotted by the receiving device. This invention describes a method to solve this problem for cases where the processor has a data bus wider than the width of the data to be transferred (this is often the case where the processor implements a general-purpose peripheral bus to which many types of peripheral devices are attached). The advantages of the invention are a resulting error detection capability better than simple parity protection, and a low cost of implementation in terms of processor computation and receiver logic.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 1

Data integrity on parity-less buses

     A number of processors do not implement parity on data buses. This can lead to errors in operation or corruption of data as errors during data transfer cannot be spotted by the receiving device. This invention describes a method to solve this problem for cases where the processor has a data bus wider than the width of the data to be transferred (this is often the case where the processor implements a general-purpose peripheral bus to which many types of peripheral devices are attached). The advantages of the invention are a resulting error detection capability better than simple parity protection, and a low cost of implementation in terms of processor computation and receiver logic.

     Consider the case where a processor implements a data bus n bytes wide, but without parity protection. The processor needs to communicate with a peripheral device on the bus where the data width to be transferred can be less than the bus width. In a simple example, the required data width is n/2 bytes. If the processor was to duplicate each byte during a write to transmit n bytes (2 sets of the n/2 required data bytes) then the receiving device could check that the byte-pairs matched before considering the write as valid, and writing away the data. In a similar manner, on a read by the processor the peripheral device could send out a duplicate data segment which could be checked by firmware on receipt.

   Specifically, the advantages are as follows: By...