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SECOND GAIN STAGE (SGS) WITH ENABLE, POLARITY REVERSAL, AND POWER DOWN FEATURES

IP.com Disclosure Number: IPCOM000013804D
Original Publication Date: 2002-May-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Abstract

Second Gain Stage (SGS) with Enable, Polarity Reversal, and Power Down Features

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  SECOND GAIN STAGE (SGS) WITH ENABLE, POLARITY REVERSAL, AND POWER DOWN FEATURES

  Second Gain Stage (SGS) with Enable, Polarity Reversal, and Power Down Features

The output stage of the Analog Front End (AFE) module designed for the Liner Tape Open (LTO) needed the capability of being tri-stated in order to be able to dot-and the outputs of more than one AFE, needed the capability to reverse the phase of the output signal, and needed to have power down capability in order to conserve power. These requirements have been achieved by one set of circuit elements reducing cost and complexity.

The circuit functions as follows. Three control signals, CHIP_SELECT, PD (power down), and NEGOUT (invert the output signal), are inputs to the circuit. A block of logic produces five output control signals, A, B, BBAR, C and CBAR. BBAR and CBAR are the logical NOT of B and C. These output control signals are related to the inputs by the following logic relations:

A = NOT(CHIP_SELECT) OR PD B = NOT(CHIP_SELECT) OR PD OR NEGOUT BBAR = NOT(B) C = NOT(CHIP_SELECT) OR PD OR NOT(NEGOUT) CBAR = NOT(C)

The input signals to the SGS, INP and INM, are connected to the bases of the output transistors Q80 and Q11 through analog switches consisting of a PFET (M33, M35, M40, M39) and an NFET (M34, M37, M46, M43) in parallel. When the signal on the gate of the PFET is low and the signal on the gate of the NFET is high, the switch is on. Then when CHIP_SELECT is high, PD is low and NEGOUT is low, meaning the chip is selected, not powered down and polarity is not negative, B is low and C is high. This means that INP is connected to the base of Q80 and INM to the base of Q11 and the output polarity is normal. If NEGOUT changes sign, B and C change sign and INP is now connected to the base of Q11 and INM to Q80 and the polarity is reversed. Note that if either CHIP_SELECT goes low or PD goes high both B and C are high and INP and INM are disconnected from the output transistors.

Simply disconnecting INP a...