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Scanning Using On-Product Clock Generation

IP.com Disclosure Number: IPCOM000013811D
Original Publication Date: 2000-Feb-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Abstract

A method to scan latches using on-product clock generation is described. Scanning of a chip in a tester environment typically uses one or more scan clocks provided by the tester, plus the scan data in and scan data out pins. A scan test could consist of a scan in operation, a test pattern, and then a scan out operation, where a test pattern consists of one or more functional clocks and other input stimulus. By using built-in self-test, the tester might only provide the functional clocks during the test pattern. One possible method of scanning uses the functional clock to do the scanning. In this case a scan mode pin is provided by the tester, which selects scan data or functional data to be loaded into the latches during a clock pulse. It is desirable to run the test pattern clocks at system speed, to ensure the chip functions at that speed. By using on-product clock generation (OPCG), it is not necessary for the tester to provide a clock at system speed. To do a scan test at system speed where the functional clock is used for scanning, it is necessary to either switch between on-chip and tester control of the clock, or to use OPCG scanning, which means the on-chip clock is clocking the latches during the scan. To use OPCG scanning in this situation, the tester could provide a scan pulse signal, which would be synchronized on chip to generate an internal scan pulse. The latches would need an additional control to hold the latch values between scan pulses. For any given pulse of the on-chip clock, the latches will be in a hold mode, scan mode, or functional mode. During the OPCG scan, each scan pulse from the tester will create a one-cycle scan mode, while at other times the latches are in hold mode. When the scan is complete, the tester would indicate the switch to functional mode, which would also be synchronized on chip. This could be used to run a built-in self-test at system speed.

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Scanning Using On-Product Clock Generation

A method to scan latches using on-product clock generation is described.

Scanning of a chip in a tester environment typically uses one or more scan clocks provided by the tester, plus the scan data in and scan data out pins. A scan test could consist of a scan in operation, a test pattern, and then a scan out operation, where a test pattern consists of one or more functional clocks and other input stimulus. By using built-in self-test, the tester might only provide the functional clocks during the test pattern. One possible method of scanning uses the functional clock to do the scanning. In this case a scan mode pin is provided by the tester, which selects scan data or functional data to be loaded into the latches during a clock pulse.

It is desirable to run the test pattern clocks at system speed, to ensure the chip functions at that speed. By using on-product clock generation (OPCG), it is not necessary for the tester to provide a clock at system speed. To do a scan test at system speed where the functional clock is used for scanning, it is necessary to either switch between on-chip and tester control of the clock, or to use OPCG scanning, which means the on-chip clock is clocking the latches during the scan.

To use OPCG scanning in this situation, the tester could provide a scan pulse signal, which would be synchronized on chip to generate an internal scan pulse. The latches would need an additional control to hold the latch values between scan pulses. For any given pulse of the on-chip clock, the latches will be in a hold mode, scan mode, or functional mode. During the OPCG scan, each scan pulse from the tester will create a one-cycle scan mode, while at other times the latches are in hold mode. When...