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CGS REDUCTION DRIVING

IP.com Disclosure Number: IPCOM000013812D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Abstract

Disclosed is a method to reduce the feed-thru voltage that causes image sticking problems. When the TFT is turned off the charge distribute to the parasitic capacitance Cgs shown in Fig.1 and result in the pixel voltage drift by ∆ Vp.(Fig.2)This voltage drift adds DC component to LC driving voltage and causes the image sticking problem. Larger storage capacitor decreases the feed-thru voltage, but lose the aperture ratio. Though the compensation pulse by next gate line is also effective to eliminate the feed-thru voltage, this compensation limits the gate drivers' driving voltage. Fig.1 Cgs : gate to source capacitance (Capacitance created by red rectangle)

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Page 1 of 4

CGS REDUCTION DRIVING

   Disclosed is a method to reduce the feed-thru voltage that causes image
sticking problems.

When the TFT is turned off the charge distribute to the parasitic capacitance Cgs

shown in Fig.1 and result in the pixel voltage drift by ∆Vp.(Fig.2)This voltage
drift adds DC component to LC driving voltage and causes the image sticking
problem. Larger storage capacitor decreases the feed-thru voltage, but lose the
aperture ratio. Though the compensation pulse by next gate line is also
effective to eliminate the feed-thru voltage, this compensation limits the gate
drivers' driving voltage.

Fig.1 Cgs : gate to source capacitance (Capacitance created by red rectangle)

Voltage

Vp

Fig.2 Feed-thru voltage
Cgs is composed of two elements.
(1) Cgs formed by the overlap between source and gate metal
(2) Cgs formed by the overlap between channel and gate metal
Component (2) is half the amount of channel capacitance, as when there is no
voltage applied between source and drain electrode, the channel charge flow
evenly to source and drain electrode.

The Poisson diagram without source-drain voltage is shown in Fig4 left. As the
source-drain configuration is symmetrical, zero field position resides in the
center between source and drain and the half amount of channel charge flow
into source and forms Cgs.

This publication discloses the method to reduce Cgs applying larger voltage to

drain electrode by ∆V when the gate voltage is turned off to have larger

1

Vp

Vg Vd

Time

[This page contains 1 picture or other non-text object]

Page 2 of 4

channel charge flow to drain electrode than source.

This effect can be calculated as follows.

Fig.4 right is the Poisson diagram when larger voltage is applied to drain by

∆V. The potential distribution can be calculated with Poisson equation,

2

dx...