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WAVEFORM BOUNCE SUPPRESSION METHOD FOR AT BUS OFF-CHIP DRIVER

IP.com Disclosure Number: IPCOM000013821D
Original Publication Date: 2000-Aug-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Abstract

Disclosed is the circuit for AT BUS Off-Chip Driver. In the design of AT BUS Off-Chip driver for 3.3V supply voltage, this negative bounce comes close to Voh. And, this negative bounce might cause malfunction. In AT/API specification, slow mode such as UDMA33 assumes C40 conductor cable which does not have shield. Because of low supply voltage, negative bounce at high level became more critical than 5V supply system. This circuit technique provides the way to suppress the negative bounce after positive transition (Fig 1-(A)). The main idea of the circuit is to control the impedance of Off-Chip driver from low impedance to high impedance in the positive transition. To achieve this, more than 2 sets of PFET should be required And, there are 2 ways to control the impedance (Fig2 and 3). Fig2 is the case we control the impedance by timing. G2 is ON in the early stage of transition and turn OFF. Total impedance is low while both G1 and G2 are ON and until G2 is OFF. The impedance becomes high after G2 OFF because only G1 is ON. Fig3 is the case we control the impedance by voltage. PFET2 in Fig3 has diode in the source node. Both PFET1 and PFET2 are ON during high output, but PFET2 becomes OFF when the output of the driver becomes VDD-Vt. In this way, the total impedance is low until PFET2 becomes OFF and becomes high afterward.

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WAVEFORM BOUNCE SUPPRESSION METHOD FOR AT BUS OFF-CHIP DRIVER

Disclosed is the circuit for AT BUS Off-Chip Driver. In the design of AT BUS Off-Chip driver for
3.3V supply voltage, this negative bounce comes close to Voh. And, this negative bounce might cause
malfunction. In AT/API specification, slow mode such as UDMA33 assumes C40 conductor cable which
does not have shield. Because of low supply voltage, negative bounce at high level became more
critical than 5V supply system. This circuit technique provides the way to suppress the negative
bounce after positive transition (Fig 1-(A)).

The main idea of the circuit is to control the impedance of Off-Chip driver from low impedance to
high impedance in the positive transition. To achieve this, more than 2 sets of PFET should be
required And, there are 2 ways to control the impedance (Fig2 and 3).

Fig2 is the case we control the impedance by timing. G2 is ON in the early stage of transition and
turn OFF. Total impedance is low while both G1 and G2 are ON and until G2 is OFF. The impedance
becomes high after G2 OFF because only G1 is ON.

Fig3 is the case we control the impedance by voltage. PFET2 in Fig3 has diode in the source node.
Both PFET1 and PFET2 are ON during high output, but PFET2 becomes OFF when the output of the driver
becomes VDD-Vt. In this way, the total impedance is low until PFET2 becomes OFF and becomes high
afterward.

Fig1-B and C is a waveform of simulation on UDMA33 with C40 conductor cable. There is a over...