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Symmetrical Clock Checker Mechanism for High Availability Systems

IP.com Disclosure Number: IPCOM000013837D
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Abstract

Disclosed is a symmetrical clock failure detection mechanism that is located in two different clock subsystems (the first one being clocked by CLK_X and the second one being clocked by CLK_Y) and that is fed by both clock sources (CLK_X and CLK_Y).

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Symmetrical Clock Checker Mechanism for High Availability Systems

Disclosed is a symmetrical clock failure detection mechanism that is located in two different clock subsystems (the first one being clocked by CLK_X and the second one being clocked by CLK_Y) and that is fed by both clock sources (CLK_X and CLK_Y).

After agreement between both subsystems on which is the active and which is the back-up, each mechanism (Figure) continuously compares clock sources coming from its own subsystem and from the other one.

If the back-up subsystem detects a clock failure, it deactivates the active one and takes the hand over by becoming the new active subsystem. An interrupt (CLK_MISS) is sent to a centralized ressource to indicate that the back-up subsystem must be replaced.

If the active subsystem detects a clock failure, an interrupt (CLK_MISS) is sent to a centralized resource to indicate that the back-up subsystem must be replaced.

2-bits Gray counter

CLK

Gray_Counter(MSB) Gray_Counter(LSB)

X

O R

D-register

CLK

CLK_MISS

D-register

CLK

monitored clock (CLK_X or CLK_Y)

supervisory clock (CLK_Y or CLK_X)

Figure

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