Browse Prior Art Database

Link Status Detection

IP.com Disclosure Number: IPCOM000013859D
Original Publication Date: 1999-Dec-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Gottfried Goldrian: AUTHOR [+2]

Abstract

The application EP 99 111 388.7 with the title „PLL Substitution by Time Measurement" describes how a coded serial signal stream can be received reliably and encoded for further processing. This logic would be also able to find out the link status of the connected port. The disadvantage of this logic is that it uses quite some space of the clock chip. Therefore there is only one for each of the 4 IETR channels. To find out the link status of all 24 IETR ports in the clock chip a logic has been invented which can find out the link status requiring only a tenth of the chip space compared to the PLL Substitution logic.

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Link Status Detection

The application EP 99 111 388.7 with the title "PLL Substitution by Time Measurement" describes how a coded serial signal stream can be received reliably and encoded for further processing. This logic would be also able to find out the link status of the connected port. The disadvantage of this logic is that it uses quite some space of the clock chip. Therefore there is only one for each of the 4 IETR channels. To find out the link status of all 24 IETR ports in the clock chip a logic has been invented which can find out the link status requiring only a tenth of the chip space compared to the PLL Substitution logic.

    The idea is to measure the minimum and maximum time between all occurring transitions of a serial coded data stream and make the result available to the controlling micro processor. This is the Cage Controller. Also if a the condition of a normal data frame or of a noisy environment is detected an attention to the Cage Controller is generated. The idea is now to support all these functions with a minimum of logic which is self contained and requires only minimum of Cage Controller interference.

Micro Proc. Interface

(Sense & Control)

Logic Clock

Edge Pulse

Coded Signal

Clock

Clock

Reset

T

Time

Counter

T > 8*n

A

Min_Time

Counter

Set: 1...1

+1

-1

Min_Value

Max_Value

Set_Counter

Edge

Compare Detector

T < A

T

A

carry

Compare

B >= 2A

A

B

Attention

B

Max_Time

Counter

Set: 0...0

+1

-1

Compare

T > B

B

T

Figure 1: Link Status Detection

    In figure 1 is the principle of the invention demonstrated. Any transition in the signal stream is converted to an Edge Pulse by the Edge Detector. This pulse causes a reset in the Time Counter (T). The latest value of T before the reset occurred is compared by the two connected comparators. The comparator at the top is comparing T with the contents of the Min_Time Counter (A). If the value of T is less than the contents of A then the counter A is incremented because the output of the comparators are enabled...