Browse Prior Art Database

A SCHEDULER USED TO SYNCHRONIZE SYSTEM/SERIAL CLOCK

IP.com Disclosure Number: IPCOM000013861D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 4 page(s) / 79K

Publishing Venue

IBM

Related People

Bernard Desrosiers: AUTHOR [+4]

Abstract

A SCHEDULER USED TO SYNCHRONIZE SYSTEMISERIAL CLOCK I. INTRODUCTION In communication products two clock domains have to speak to each other: a bit clock domain for the transmission lines and a "multi bits", Le. 16 or 32 bits clock domain for the micro controller side. These two clocks, usually named SERIAL and SYSTEM clocks, are a synchronous. Special devices have to be used to insured a proper flow for the data between theses two domains. There are often names "synchronize device". The disclosed devices are part of these. II. DESCRIPTION

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A SCHEDULER USED TO SYNCHRONIZE SYSTEM/SERIAL CLOCK

A SCHEDULER USED TO SYNCHRONIZE SYSTEMISERIAL CLOCK

I. INTRODUCTION

In communication products two clock domains have to speak to each other: a bit clock domain for the transmission lines and a "multi bits", Le. 16 or 32 bits clock domain for the micro controller side. These two clocks, usually named SERIAL and SYSTEM clocks, are a synchronous. Special devices have to be used to insured a proper flow for the data between theses two domains. There are often names "synchronize device". The disclosed devices are part of these.

II. DESCRIPTION

An usual way of handling this synchronization problem is to synchronize the slower clock, Le. serial one against the faster clock,
i.e. the system one. This method has several inconveniences mainly because it is difficult to have différent clock frequency domains which cohabit on the same chip especially to perform timing analysis.

The disclosed idea is to use a system clock counter triggered by the serial clock. The counter ouputs are used to gate the propagation of the data through the logic. Figure 1 shows a typical block diagram and figure 2 shows a timing chart example.

1

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Figure 1: Block Diagram Timing chart

2

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A SCHEDULER USED TO SYNCHRONIZE SYSTEM/SERIAL
CLOCK - Continued

Figure 2: Timing chart

III. SCHEDULER BEHAVIOR

The scheduler, shown on figure 1, is a system
clock counter. It is triggered...