Browse Prior Art Database

I/O DEVICE ERROR PROCESSING IN A MULTI-THREADED INSTRUCTION-UNIT DESIGN

IP.com Disclosure Number: IPCOM000013873D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-18
Document File: 1 page(s) / 52K

Publishing Venue

IBM

Related People

Ken Tsuchiya: AUTHOR [+4]

Abstract

This disclosure shows a solution for handling IO device errors in a Multithreaded (two threads) Super-Scalar processor design.

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This is the abbreviated version, containing approximately 100% of the total text.

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  I/O DEVICE ERROR PROCESSING IN A MULTI-THREADED INSTRUCTION-UNIT DESIGN

This disclosure shows a solution for handling IO device errors in a Multithreaded (two threads) Super-Scalar processor design.

The design handles IO device errors per thread base as if each thread is independent process based on the thread Machine-State-Register designator, namely Machine-Check-Enable state, which designates whether the error is processed as a fault type (non-recoverable) or non-fault type(recoverable), with using a common/shared "FRU(Field-Replaceable-Unit) error process and capture" unit and other resources. Although the mechanism is shown as an asynchronous IO error handling method, it can be used in any asynchronous device interfaces for status capturing and other functions in a Multithreaded processor design.

(HARDCOPY FIGURES NOT AVAILABLE)

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