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A Data Communications System with Hidden Squelch Suppress Function for Improved Testability of the Receive Channel

IP.com Disclosure Number: IPCOM000013908D
Original Publication Date: 2001-Mar-16
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Abstract

Disclosed is a circuit which will provide a hidden squelch suppression function for a data communications system, this enables improved testability of the receive channel with the advantage that it can only be operated during testing of the system and not in normal introduction. Introduction Within digital data communication systems, a transmitter is connected to a receiver through a transmission channel media such as an electrical cable or optical fibre. It is well known that the transmitted data will experience an error rate which will increase as the loss through the media increases. In practical systems, a threshold level is often set at the receiver below which the receiver will not process the incoming signal and this can be referred to s the 'squelch' level. Within digital communication applications, the squelch level can be used to ensure that the receiver will always be capable of attaining a bit error rate specification. If the signal into the receiver is low then the reduced signal to noise ratio will increase the probability of errors occurring and therefore degrade the bit error rate. However by setting the squelch level at an appropriate level, the receive channel can detect whether the incoming signal will satisfy a specified error rate performance. If the signal is too low, an error signal can be set on the system to ensure that the received data is not used. In the example shown in Figure 1, the output of a signal level detector is used to gate the output of the receiver. When the input signal is below the threshold of the level detector, the output of the receiver is gated off and the error signal is set. Figure 1

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  A Data Communications System with Hidden Squelch Suppress Function for Improved Testability of the Receive Channel

    Disclosed is a circuit which will provide a hidden squelch suppression function for a data communications system, this enables improved testability of the receive channel with the advantage that it can only be operated during testing of the system and not in normal introduction.

Introduction

Within digital data communication systems, a transmitter is connected to a receiver through a transmission channel media such as an electrical cable or optical fibre. It is well known that the transmitted data will experience an error rate which will increase as the loss through the media increases. In practical systems, a threshold level is often set at the receiver below which the receiver will not process the incoming signal and this can be referred to s the 'squelch' level. Within digital communication applications, the squelch level can be used to ensure that the receiver will always be capable of attaining a bit error rate specification. If the signal into the receiver is low then the reduced signal to noise ratio will increase the probability of errors occurring and therefore degrade the bit error rate. However by setting the squelch level at an appropriate level, the receive channel can detect whether the incoming signal will satisfy a specified error rate performance. If the signal is too low, an error signal can be set on the system to ensure that the received data is not used. In the example shown in Figure 1, the output of a signal level detector is used to gate the output of the receiver. When the input signal is below the threshold of the level detector, the output of the receiver is gated off and the error signal is set.

Figure 1

When the receiver is tested, for example during manufacturing, it is important to ensure that it operates correctly down to the specified minimum input signal at which the squelch circuit op-erates. In modern data communication systems, the bit error rate specification could typically be 1E-13 for a system with a data rate of 1Gb/s. This would mean that the receiver would need to be operated for at least 10000 seconds during test to ensure that an error had not occurred and that the bit error rate specification was satisfied. In many applications, this would be an impractically long test period and this disclosure describes how a much shorter test time can be achieved without affecting normal operation of the system by:

Increasing the loss of the transmission media during testing such that the error rate could be conveniently measured within a reasonable time interval. With knowledge on how the bit error rate varies with path loss ( or input signal level ), extrapolation on this characteristic can be used to calculate the bit error rate when a specified path loss

Disabling the squelch circuit during the test to allow the receiver to be tested with an input signal which has a poorer signal t...