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Method and apparatus for achieving consistency in a multiprocessor

IP.com Disclosure Number: IPCOM000013917D
Original Publication Date: 2001-Mar-30
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Abstract

Reordering of memory operations and renaming of memory locations into on-chip registers require significant resources to maintain multiprocessor coherence. In particular, memory accesses which have been re-ordered, or memory addresses which have been renamed into physical registers need to be tracked in reference to the memory traffic from other processors.

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Method and apparatus for achieving consistency in a multiprocessor

Reordering of memory operations and renaming of memory locations into on-chip registers require significant resources to maintain multiprocessor coherence. In particular, memory accesses which have been re-ordered, or memory addresses which have been renamed into physical registers need to be tracked in reference to the memory traffic from other processors.

This tracking usually involves coherence actions such as snooping of bus traffic, lookup of tags in memory order buffers, and invalidation of out-of-order accesses as well as restarting the processor at a point prior to the invalidated out-of-order memory operations which have been invalidated.

If aggressive out-of-order execution and renaming of memory references occurs, this can impose significant cost on the tracking of such operations, even if they are never the subject of any coherence actions because they refer to data private to a single processor.

The size of tables used for coherence preservation and the performance of such coherence processing can be improved by excluding private data from multi-processor coherence tables and snooping accesses. In particular, load- and store operations which have been executed out-of-order need not be snooped relative to other processors if they refer to private address space ranges.

In a preferred embodiment, the operating system should designate such private address ranges which should be of large granularity, i.e., at least page size or larger (e.g., segments). Embodiments can use either page table entry fields or special processor resources (e.g., special purpose registers) for designating private address ranges.

Following this strategy, access to a processor's private address ranges can be performed using onl...