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GENERATION OF A DIFFERENTIAL LOW LEVEL TEST SIGNAL WITH A COMMON MODE DC VOLTAGE VALUE FROM A STANDARD TTL LOGIC SIGNAL

IP.com Disclosure Number: IPCOM000013920D
Original Publication Date: 2000-Feb-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Abstract

In many applications there is a requirement to generate a low level differential signal with a given "common mode" DC voltage level. These signals are used for internal test of analog electronic modules and for verification of wiring interconnect between modules.

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  GENERATION OF A DIFFERENTIAL LOW LEVEL TEST SIGNAL WITH A COMMON MODE DC VOLTAGE VALUE FROM A STANDARD TTL LOGIC SIGNAL

In many applications there is a requirement to generate a low level
differential signal with a given "common mode" DC voltage level. These signals
are used for internal test of analog electronic modules and for verification
of wiring interconnect between modules.

Shown above is the circuit diagram for the generation of the test signal. This
generated test signal is called Long Loop Write to Read (LLWR). The input to
the circuit, called LLWR_IN, is connected to a TTL receiver circuit which is
capable of receiving a TTL signal sent from some off chip source. The TTL
receiver will convert the signal from a TTL level to a CMOS level that moves
from ground to VCC depending on whether it is a logic 0 (at ground) or a logic
1 (at VCC).

Devices M202/M206 and M201/M205 function as CMOS inverters If LLWR_IN is a
logic 1 (at VCC) then Node A will be at logic 0 (at ground) and Node B will be
a logic 1 (at VCC). Devices M1/M2 and M7/M5 also function as CMOS inverters.
For our same condition of LLWR_IN at a logic ,1 Node C will be a logic 1 (at
VCC) and Node D will be a logic 0 (at ground). Inverters M1/M2 and M7/M5 have

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been "sized" to allow for a current flow through the resistor string R21, R20,
R19, R12, R9, R22, R11, R10, R13, R18, R17, and R16. There will be a current
flow through the resistor strin...