Browse Prior Art Database

Fully Controllable Two-phase Clock Splitter

IP.com Disclosure Number: IPCOM000013964D
Original Publication Date: 2000-Aug-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Abstract

Disclosed is a new clock splitter circuit whose split outputs, called C-clock and B-clock here, can be fully independently controlled.

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Fully Controllable Two-phase Clock Splitter

   Disclosed is a new clock splitter circuit whose split outputs, called
C-clock and B-clock here, can be fully independently controlled.

   In recent big, high-density chips, separate control of C-clock and B-clock
is, as well known, important in effectively saving power consumption and still
making macros or circuit blocks ready for fast recovery and operation at an
appropriate timing by stopping internal clocks and, at the same time, running
macros' or blocks' input interface circuits' clock which is C-clock or B-clock
depending on which clock is used in the input interface circuits.

Fig.1 shows the disclosed new clock splitter circuit.

Fig.1

The input "GATE1" is used to force the output C-clock "ZC" to a "L" level, and
the input "GATE2" is used to force the output B-clock "ZB" to the "L" level.
Here it is assumed that the inactive state of the split clocks is given by the
"L" level. "OSC" is the user clock input before splitting. "C" and "B" are
the test clock inputs for scan testing. In users' functional mode, "C" and
"B" are held at a "H" level, and "GATE1" and "GATE2" are used to control "ZC"
and "ZB" independently each other. In scan test mode, "OSC" is held at the
"L" level and "GATE1" is held at the "H" level.

Fig.2 shows one of conventional clock splitters.

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Fig.2

In this circuit, the input "GATE" is forced at the "L" level in the user
functional mode, and a...