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Serial data transfer with extra clock check

IP.com Disclosure Number: IPCOM000013992D
Original Publication Date: 2001-Jan-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Abstract

Disclosed is the method to avoid serial data transfer error between modules on a PCB.

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Serial data transfer with extra clock check

Disclosed is the method to avoid serial data transfer error between modules on a PCB.

As LSI technology is getting faster, rising time and falling time of the waveform from the

LSI is getting faster. That means increase of reflection and crosstalk. If the distortion

of the waveform caused by the reflection and the crosstalk goes over a logic threshold

level, data can not be transferred correctly.

In fig.1 typical data transfer format between modules on a PCB is shown.

During IP ENABLE is active, IP DATA is read at rising edge of IP CLK. If IP CLK has too large distortion, IP DATA can not be read correctly.

The proposed method counts the number of IP CLK and if the number is different from predetermined number, a receiver of data sends error status to a sender. The method to send error status is done by a existing line. The example of the transfer sequence is as follows.

In this example, IP ENABLE is used to send the error status.

1. After sending all data, the sender deactivates IP ENABLE.
2. The sender makes IP ENABLE hi-impedance.
3. The receiver checks number of IP CLK and if the number is different, the receiver

activate IP ENABLE for predetermined period during IP ENABLE is hi-impedance.
4. The sender check IP ENABLE at predetermined time and if it is active, the sender

send the same data for retry purpose.

By this sequence, reliable data transfer can be achieved.

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