Browse Prior Art Database

Prediction of I/O Sequential Data Access to Enable Enhanced System Performance

IP.com Disclosure Number: IPCOM000013995D
Original Publication Date: 2000-Oct-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

Prediction of I/O Sequential Data Access to Enable Enhanced System Performance

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Prediction of I/O Sequential Data Access to Enable Enhanced System

Performance

Disclosed is a method to enhance I/O performance, and therefore system performance, by performing a predictive fetch of the I/O translation information and data.

In systems where 32-bit I/O devices must access 64-bit address spaces, it is necessary to have some sort of translation mechanism in the bridges to translate the 32-bit to 64-bit address. If this is not to be a fixed translation (which has many restrictions) then a dynamic method must be used, and such is the case in PowerPC platforms. In these systems a Translation Control Entry (TCE) is associated with each four kilobyte block of address space and this determines which I/O bus four kilobyte page will access which System Memory four kilobyte page. These TCEs are generally fetched when the devices first accesses a new page. The TCEs themselves are stored in system Memory, and there is a latency associated with the fetching of the TCE. This latency reduces I/O performance.

Some transfers from memory to I/O tend to be very sequential in nature. The method described in this disclosure gets around the need for the software to tell the hardware of data sequentiality, while maintaining the look-ahead performance advantage of prefetching ahead of when the I/O needs the data. It does this by detecting the sequential access of the last four 512-byte blocks on a page of memory, and prefetches the next TCE automatically in parallel with the I/O device accessing the last 512-byte block of the page. This could be extended to more than four blocks, should the implementation deem there to be a need to increase the probability of the sequential prediction algorithm being correct.

The method is as follows:

1. Add 2 bits per TCE in the TCE cache

2. When an IOA accesses an address of x....x100000000000...