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A Method for Verifying the Correct Ordering of MMIOs and Invalidation Requests Across an IO Bridge

IP.com Disclosure Number: IPCOM000014068D
Original Publication Date: 2001-Sep-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Abstract

A Method for Verifying the Correct Ordering of MMIOs and Invalidation Requests Across an IO Bridge Disclosed is an algorithm that efficiently verifies that processor storage accesses to IO devices (i.e. Memory mapped IOs or MMIOs) and processor invalidation requests to IO caches (i.e. Kill requests) are ordered correctly across an IO bridge. The algorithm uses a simulation of IO cache directories to quickly determine when it is required for a Kill request to propagate across an IO bridge, and then verifies that this Kill request is ordered the same way with MMIO requests on either side of the bridge. The algorithm is designed to work in a simulation environment that emulates hardware function via software simulation directly based on hardware specifications.

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A Method for Verifying the Correct Ordering of MMIOs and Invalidation Requests

Across an IO Bridge

Disclosed is an algorithm that efficiently verifies that processor storage accesses to IO devices
(i.e. Memory mapped IOs or MMIOs) and processor invalidation requests to IO caches (i.e. Kill requests) are ordered correctly across an IO bridge. The algorithm uses a simulation of IO cache directories to quickly determine when it is required for a Kill request to propagate across an IO bridge, and then verifies that this Kill request is ordered the same way with MMIO requests on either side of the bridge. The algorithm is designed to work in a simulation environment that emulates hardware function via software simulation directly based on hardware specifications.

For some IO devices, it is possible for a storage access from a processor to an IO device (i.e. an MMIO) to cause the IO device to initiate a DMA (Direct Memory Access) Read. This cause and effect relationship produces a system wide ordering between the MMIO and the DMA -- the processor and IO device should behave as if the DMA came after the MMIO. Thus, data returned by the DMA read should be at least as up-to-date as the last store to the cacheline of the DMA from the processor.

To ensure that this ordering is upheld, many IO controllers impose the following rule: a storage access by a single processor to an IO device (an MMIO) may not pass any invalidation requests previously sent by that processor. Given the fact that any processor stores will cause an kill request to be sent to all IO devices that have the line/page of the address locally cached, the rule guarantees that DMA reads following MMIOs will not hit in any local IO cache if the cached line/page in IO has older data than that of any stores by the processor that preceded the MMIO. The algorithm was designed in a verification environment that provides a database of simulation activity. The algorithm depends on several of the services this database provides. Among these services are:

1). The database contains information about all bus transactions that may affect the data hierarchy of the system that occurred on the system and IO busses during simulation. At a minimum, for each of these transactions the following information must be present: Transaction type, issue time, address.

2). The database contains a list of all cachelines referenced by transactions that occurred during simulation on either of these busses.

3). The database provides a mechanism to allow the algorithm to access bus transactions in some ordered manner. This order can depend on any or all of the following criteria: cacheline, source bus, source device, issue time.

4). The database provides mechanisms for determining which IO bus transactions are related to which System Bus transactions. As an example, suppose an IO device does a DMA read. In certain system c...