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Method and apparatus for maximizing availability of an embedded dynamic memory cache.

IP.com Disclosure Number: IPCOM000014077D
Original Publication Date: 2001-Apr-26
Included in the Prior Art Database: 2003-Jun-19
Document File: 4 page(s) / 52K

Publishing Venue

IBM

Abstract

In a processor using embedded dynamic random access memory (DRAM) for an on-chip cache, availability of the cache is compromised by the need to periodically refresh the array. It is desirable to maximize the availability of the array for accesses by the processor by refreshing the array as infrequently as possible. However, it is not acceptable to lose data stored in the array. Therefore, a solution is required that maximizes the availability of an embedded DRAM array by extending the refresh period while maintaining the integrity of the data by avoiding data loss due to an excessive period between refreshes. This invention uses error detection and correction circuitry to monitor the onset of data loss due to inadequate refresh (hereafter called "refresh failures") and a variable-period timer to adjust the refresh period to a point just short of the onset of refresh failures. The simplest and densest memory cell is the DRAM cell using a single transistor and a storage capacitor (see Fig. 1) below. Embedded dynamic memory is an attractive choice for an on-chip cache for a processor since it is more dense than a static memory. Using DRAM technology, a larger array can be used for the same area and power, or the same logical size (bit capacity) can be implemented requiring less chip area and power. One complication, however, is that DRAM arrays require periodic refresh in order to avoid losing stored data. Since the memory array cannot simultaneously perform a refresh and a read or write access, the time required to perform the refresh subtracts directly from the time the dynamic memory is available to service access request from the processor. Minimizing the amount of time the dynamic memory is refreshing improves the performance of the system by maximizing the array availability. DRAM cells which are defective in some way (leakage is higher through the capacitor or pass transistor) generally fail first if the period between refreshes is extended. Manufacturing defects often result in a shorter refresh period requirement in a few cells that fail long before the majority of the cells. Error detection and correction (EDC) is used to improve the reliability of large memory arrays. Single-bit errors are correctable and multiple-bit errors are detectable in a minimal EDC design. The invention describes a system in which the refresh period of an on-chip dynamic memory array is varied, increasing the period as much as possible to maximize availability, and using EDC to detect (and correct) the onset of data loss due to inadequate refresh.

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  Method and apparatus for maximizing availability of an embedded dynamic memory cache.

    In a processor using embedded dynamic random access memory (DRAM) for an on-chip cache, availability of the cache is compromised by the need to periodically refresh the array. It is desirable to maximize the availability of the array for accesses by the processor by refreshing the array as infrequently as possible. However, it is not acceptable to lose data stored in the array. Therefore, a solution is required that maximizes the availability of an embedded DRAM array by extending the refresh period while maintaining the integrity of the data by avoiding data loss due to an excessive period between refreshes.

This invention uses error detection and correction circuitry to monitor the onset of data loss due to inadequate refresh (hereafter called "refresh failures") and a variable-period timer to adjust the refresh period to a point just short of the onset of refresh failures.

The simplest and densest memory cell is the DRAM cell using a single transistor and a storage capacitor (see Fig. 1) below. Embedded dynamic memory is an attractive choice for an on-chip cache for a processor since it is more dense than a static memory. Using DRAM technology, a larger array can be used for the same area and power, or the same logical size (bit capacity) can be implemented requiring less chip area and power. One complication, however, is that DRAM arrays require periodic refresh in order to avoid losing stored data. Since the memory array cannot simultaneously perform a refresh and a read or write access, the time required to perform the refresh subtracts directly from the time the dynamic memory is available to service access request from the processor. Minimizing the amount of time the dynamic memory is refreshing improves the performance of the system by maximizing the array availability. DRAM cells which are defective in some way (leakage is higher through the capacitor or pass transistor) generally fail first if the period between refreshes is extended. Manufacturing defects often result in a shorter refresh period requirement in a few cells that fail long before the majority of the cells.

Error detection and correction (EDC) is used to improve the reliability of large memory arrays. Single-bit errors are correctable and multiple-bit errors are detectable in a minimal EDC design. The invention describes a system in which the refresh period of an on-chip dynamic memory array is varied, increasing the period as much as possible to maximize availability, and using EDC to detect (and correct) the onset of data loss due to inadequate refresh.

Figure 1.

Data is written to a DRAM cell by charging (or discharging) the capacitor when the pass device is conducting and the bit line (BL) is held high (or low). Data is read from a DRAM cell by allowing the BL to "float", turning on the pass gate, and then sensing the voltage excursion of the BL due to charge sharing...