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Merged Branch Prediction Algorithm and Array Word Line Decode.

IP.com Disclosure Number: IPCOM000014162D
Original Publication Date: 2001-Apr-26
Included in the Prior Art Database: 2003-Jun-19
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Abstract

Disclosed is a method to improve performance of branch prediction circuitry by merging the prediction algorithm with the array word line decoders. This method does not require the branch prediction algorithm to produce a binary encoded value to address an array where branch prediction information is stored. In the new method the branch prediction algorithm is altered so that decoded array word lines are directly realized.

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Merged Branch Prediction Algorithm and Array Word Line Decode.

    Disclosed is a method to improve performance of branch prediction circuitry by merging the prediction algorithm with the array word line decoders. This method does not require the branch prediction algorithm to produce a binary encoded value to address an array where branch prediction information is stored. In the new method the branch prediction algorithm is altered so that decoded array word lines are directly realized.

As branch prediction algorithms become more complex, and processor speeds increase the need to do branch prediction more efficiently has become necessary. In a traditional super-scalar processors information used to do branch prediction is first gathered to a central point. This information is usually the program counter value of the branch instruction, a global history vector of past branch directions, and other processor status information. The other processor status may be the last data value loaded, condition register bits, or other processor registers. This information is then compacted using some algorithm into a binary value used to index into an array. There has been much academic literature on algorithms and processor status information used to produce this binary encode. The array then takes the binary encoded address and decodes it into word lines to access array elements. The array elements contain branch history patterns or saturating counters used to predict branch direction. It is desirable to be able to perform this operation in one processor cycle and not have this function gate processor cycle time.

Fig. 1 shows a traditional branch predictio...