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WIDE COMPARE STAGE EQUALIZATION TECHNIQUE FOR CONTENT ADDRESSABLE MEMORIES

IP.com Disclosure Number: IPCOM000014175D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 1 page(s) / 53K

Publishing Venue

IBM

Related People

Pete Freiburger: AUTHOR [+4]

Abstract

Wide compares across many bits are common in content addressable memory (CAM) designs. These compares usually need to have good performance. This is a technique for equalizing the loading on multiple dynamic stages to improve the performance of the compare. The method improves the performance by decreasing the loading on the miss line and increasing the loading on c1 by having two bits share a c1 as shown below in Fig. 1. This will produce a faster output because we are equalizing the loading of the stages.

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  WIDE COMPARE STAGE EQUALIZATION TECHNIQUE FOR CONTENT ADDRESSABLE MEMORIES

Wide compares across many bits are common in content addressable memory (CAM) designs. These compares usually need to have good performance. This is a technique for equalizing the loading on multiple dynamic stages to improve the performance of the compare. The method improves the performance by decreasing the loading on the miss line and increasing the loading on c1 by having two bits share a c1 as shown below in Fig. 1. This will produce a faster output because we are equalizing the loading of the stages.

This can be extended further as shown in Fig. 2.

(HARDCOPY FIGURES NOT AVAILABLE)

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