Browse Prior Art Database

Supporting Summary Overflow in the Power 4 Processor Core

IP.com Disclosure Number: IPCOM000014194D
Original Publication Date: 2000-Mar-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Abstract

The disclosed method maintains the Summary Overflow (SO) bit of the Fixed Point Exception Register (XER) in the Power 4 microprocessor core. The Power 4 core, an out-of-order execution, superpipelined, superscalar microprocessor, implements the PowerPC/AS Instruction Set Architecture. This out-of-order nature makes implementation of any summary or sticky status bits, such as Summary Overflow, very difficult.

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Supporting Summary Overflow in the Power 4 Processor Core

The disclosed method maintains the Summary Overflow (SO) bit of the Fixed Point Exception Register (XER) in the Power 4 microprocessor core. The Power 4 core, an out-of-order execution, superpipelined, superscalar microprocessor, implements the PowerPC/AS Instruction Set Architecture. This out-of-order nature makes implementation of any summary or sticky status bits, such as Summary Overflow, very difficult.

This method uses the existing tools of group interrupt boundaries and instruction flush mechanisms to maintain an architecturally correct view of SO. Through repeated 'divide and conquer' flushes (purges) of instructions, the processor identifies the instruction that causes SO to change. It then forces all subsequent instructions to execute with the correct value of SO.

Initially, the processor decodes and groups instructions that may cause SO to change without any special rules or restrictions. The instruction that causes SO to flush executes within the Fixed Point Unit (FXU). The FXU maintains two copies of SO: the working copy and the architect copy. The FXU examines the working copy of SO to determine if SO needs to be changed based on the currently executing instruction. When the FXU executes an instruction that must change SO, it reports this to the Global Completion Table (GCT). The GCT notes which group has an instruction that needs to change SO. (Within the Power 4 core, instructions are tracked in groups of up to four non-branch instructions plus one branch instruction.)

Once the GCT identifies a group that needs to change SO, it checks the group to see if there is only one instruction in the group, and that the instruction is not Move to Condition Register from XER, "mcrxr". "mcrxr" is the only PowerPC/AS instruction that reads SO before it updates SO; all other instructions read SO after it is modified. Since the instruction was originally grouped with its neighboring instructions, it may not be alone in the group. The GCT flushes (or purges) that group of instructions. This flush signals to the fetch logic to refetch starting with the first instruction in the flushed group. The instructions that were in the flushed group are now dispatched in single instruction group mode. This mode forces each PowerPC/AS instruction into a group by itself.

The instruction that causes SO to change is now in a group by itself. The FXU again execut...