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Synchronous Data Transfer for high data rate support

IP.com Disclosure Number: IPCOM000014211D
Original Publication Date: 1999-Oct-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 1 page(s) / 27K

Publishing Venue

IBM

Related People

Katsuhiko Katoh: AUTHOR [+2]

Abstract

This article describes a high data transfer rate support method at lower system clock(RDWTCLK faster than system clock) by synchronous data transfer between channel to ECC(Error Correction Code) Logic.

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Synchronous Data Transfer for high data rate support

This article describes a high data transfer rate support method at lower system clock(RDWTCLK
faster than system clock) by synchronous data transfer between channel to ECC(Error Correction
Code) Logic.

The block diagram of the high data rate transfer support method is shown as Figure.
RDWTCLK is clock from read/write channel that is used for transfer between DRIVE CONTROL Logic
and CHANNEL. NRZBUS is 8bit non return to zero data. DRIVE CONTROL logic transfers NRZBUS to/from
CHANNEL synchronized to RDWTCLK. When ECC's field is same as NRZBUS's width , RDWTCLK that is
faster than system clock can support by synchronize Parity encoder portion and Syndrome generator
portion to RDWTCLK. By above description, high data transfer rate is supportable with no gate
increase.(i.e. Parity encoder and Syndrome generator is not doubled or system clock that is faster
than RDWTCLK is not required.)

In write operation, DRIVE CONTROL logic transfers NRZBUS to CHANNEL and DATA to Parity encoder in ECC logic
synchronize to RDWTCLK. After parity generation, ECC logic transfers Parity to DRIVE CONTROL logic, then
DRIVE CONTROL logic transfers Parity to CHANNEL on NRZBUS synchronize to RDWTCLK. In this operation, system
clock does not affect NRZBUS data transfer rate.

In read operation, CHANNEL transfers NRZBUS to DRIVE CONTROL logic, then DRIVE CONTROL logic transfers DATA
same as NRZBUS to Syndrome generator in ECC logic synchronize to RDWTCLK....