Browse Prior Art Database

DUTY CYCLE CHECKER FOR HIGH FREQUENCY SIGNALS

IP.com Disclosure Number: IPCOM000014212D
Original Publication Date: 2001-Apr-09
Included in the Prior Art Database: 2003-Jun-19
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Abstract

DUTY CYCLE CHECKER FOR HIGH FREQUENCY SIGNALS In digital systems, some control signals such as reference clocks have a set of input requirements at Very Large Scale Integration circuit interface. One requirement is related to the ratio of the time at high state (or low state) with respect to the signal period, T0, also called Duty Cycle (DC). A common typical value is 50 with an allowed dispersion of a few percent. For high reliability operation , it is key to continuously check that this requirement is still met.

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DUTY CYCLE CHECKER FOR HIGH FREQUENCY SIGNALS

DUTY CYCLE CHECKER FOR HIGH FREQUENCY SIGNALS

In digital systems, some control signals such as reference clocks
have a set of input requirements at Very Large Scale Integration
circuit interface.

One requirement is related to the ratio of the time at high state
(or low state) with respect to the signal period, T0, also called
Duty Cycle (DC). A common typical value is 50 % with an allowed
dispersion of a few percent.

For high reliability operation , it is key to continuously check
that this requirement is still met.

For low frequency signals with a period of T0, a solution is to
use a higher frequency signal with a period at least 100 times
smaller than T0. A digital circuit counting the number of
occurrences of the signal at high (or low) state , provides the
checking function.

A + or - 5% tolerance would lead to a number of allowed samples
between 45 and 55 if the frequency ratio of the two signals is
100. Such a technique is based on the availability of a signal at
much higher frequency than the signal to be checked. This
situation does not occurs very often in electronic sub assemblies
working at high frequencies , typically several hundred of
megahertz.

What is disclosed is a simple electronic device able to check any
kind of duty cycle requirement at any frequency.

The signal to be checked (1) is applied to a buffer circuit (2).
The only requirement for the buffer is to be fast enough to be
compatible with the input signal bandwidth.

The buffer is characterised by it's output impedance Rout. The
buffer output is loaded by an external capacitor C such that the
time constant Rout*Cis significantly higher than T0.

An order of magnitude may be : Rout*C=100*T0.

The buffer output exhibits a saw too...