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CIRCUITRY AND METHOD FOR EVALUATING THE SPEED OF ASIC SEMICONDUCTOR DEVICE CIRCUITRY

IP.com Disclosure Number: IPCOM000014251D
Original Publication Date: 2000-Feb-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

High Performance ASIC semiconductor devices are designed to operate within a predefined range of speed which is based on an ASIC's design and the speed of the components that comprise the ASIC device. Variations in ASIC fabrication both controlled and uncontrolled account for differences in speed of the components of one ASIC as compared to another ASIC having the same design and technology. These variations in speed may cause an ASIC to be rejected for use when it operates beyond the acceptable range of speed specified by the design, i.e., it operates either too fast or too slow. To assist manufacturing and/or development in identifying the speed of an ASIC, an ASIC may include performance circuitry and additional signal inputs/outputs (i/o's) which provide access to this circuitry. Given these, an ASIC's speed can be determined by contacting an external measuring device to these special i/o's. Disadvantages of this method are: Assignment of chip/die i/o's for performance measurement causes a reduction in the number of available signal i/o's to be used by the ASIC design. Product cost increases if a larger ASIC must be selected to accommodate required performance i/o's. Propagation of performance signal i/o's to "highest" level of package inflates cost of packages in addition to the ASIC. Performance monitoring i/o's may not be accessible post manufacturing assembly, making measurement impossible.

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  CIRCUITRY AND METHOD FOR EVALUATING THE SPEED OF ASIC SEMICONDUCTOR DEVICE CIRCUITRY

    High Performance ASIC semiconductor devices are designed to operate within a predefined range of speed which is based on an ASIC's design and the speed of the components that comprise the ASIC device. Variations in ASIC fabrication both controlled and uncontrolled account for differences in speed of the components of one ASIC as compared to another ASIC having the same design and technology. These variations in speed may cause an ASIC to be rejected for use when it operates beyond the acceptable range of speed specified by the design, i.e., it operates either too fast or too slow. To assist manufacturing and/or development in identifying the speed of an ASIC, an ASIC may include performance circuitry and additional signal inputs/outputs (i/o's) which provide access to this circuitry. Given these, an ASIC's speed can be determined by contacting an external measuring device to these special i/o's. Disadvantages of this method are:

Assignment of chip/die i/o's for performance measurement causes a reduction in the number of available signal i/o's to be used by the ASIC design. Product cost increases if a larger ASIC must be selected to accommodate required performance i/o's.

Propagation of performance signal i/o's to "highest" level of package inflates cost of packages in addition to the ASIC.

Performance monitoring i/o's may not be accessible post manufacturing assembly, making measurement impossible.

If measurements are possible following manufacturing assembly, system disassembly and special instrumentation is usually required to reach performance contact points.

When disassembly is required, environmental characteristics change with disassembly which may affect measurement accuracy.

Labeling of each ASICs performance is expensive, cumbersome, and error prone.

The subject invention provides a means whereby the speed of circuitry within an ASIC chip is measured by circuitry provided within the ASIC itself, and once measured, its speed is communicated via an interface accessible to software. Also, provided is a means whereby the ASIC determines whether or not it operates within an acceptable performance range, based on provided delay values.

Coupled to an on-chip Performance Screen Ring Oscillator (PSRO) chain is a device which measures the circuit delay and converts the measured delay value to a digital symbol which is stored in an on-chip register, known as the Delay Register. The preferred embodiment of the invention provides for continual performance sense and update of the Delay Register. To observe the contents of the Delay Register, the register is accessed by software by either a long scan, a scan communication read via a JTAG IEEE 1149.1 interface, or by a request received from some other off-chip interface. A request of this type causes the requested contents of the Delay Register to be returned to the interface from which the request origi...