Browse Prior Art Database

Method for testing trace arrays using minimal logic and control inputs

IP.com Disclosure Number: IPCOM000014287D
Original Publication Date: 2001-Apr-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Abstract

The brief concept employed in this disclosure on testing of arrays embedded into VLSI chips is simply stated "one does not necessarily require complete testing of all possible circuit function when the actual usage of the circuit does not encompass the entire function of the circuit". Furthermore, blinding testing of circuits without examining the intended function can lead to wasting investment resources in test overhead which do not even stress the function of the intended usage. When the design for test engineer examines the usage of the circuit, then significant hardware resources can be realized; we pay less and get an even better quality test. One example of this concept is the testing of embedded trace arrays. First of all, one familiar with the problems of testing embedded arrays on VLSI chips understands the benefits but associated costs of array "built-in" self testing, ABIST. The benefits are reduced tester-to-chip pin connections, decreased tester memory requirements, and decreased test time. The costs are increased on-chip area to implement the ABIST and design resources to implement and verify the ABIST. Secondly, one familiar with the use of trace arrays for logging signals on a VLSI chip at the on-chip clock frequency understands the intended operation of the trace arrays. The logic external to the one write-read ported trace array will initiate a singular or a burst of write operations followed by a dump of the array contents via sequential read operations. While ABIST minimally implements a "march" sequence, such as READ data at address, WRITE opposite data at address, READ opposite data at address, this READ/WRITE/READ sequence is not the functional operating sequence of the trace arrays. Trace arrays functionally use the following sequence: WRITE/WRITE/WRITE/.../READ/READ/READ. By implementing the ABIST for the trace arrays to execute the latter test sequence, the hardware real estate required is significantly reduced plus the test is exercising the actual function. Specifically, to implement ABIST, the logic design shares the address incrementer used by the functional "trace control" logic. It then adds a second incrementer of equal size to source the data. One control bit is required for the WRITE-READ control. Additional control bits may include complement address control, complement data control, ripple address control, pause test control, and test done control. One additional bit is required to hold a fail condition should unexpected data be read out of the array. The test begins with the address and data incrementers equal and the WRITE-READ control bit set to WRITE mode. With each successive WRITE, the incrementers increase by 1 until address counter is at the value for the maximum address of the array; at this cycle the WRITE-READ control is changed to READ. The address and data counters continue to increment in-step with each with each system clock issued. Again, when the address counter is at the maximum address value, the WRITE-READ control is toggled back to the WRITE mode. While the WRITE-READ control is in the READ mode, the data

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 60% of the total text.

Page 1 of 2

Method for testing trace arrays using minimal logic and control inputs

The brief concept employed in this disclosure on testing of arrays embedded into VLSI chips is simply stated "one does not necessarily require complete testing of all possible circuit function when the actual usage of the circuit does not encompass the entire function of the circuit". Furthermore, blinding testing of circuits without examining the intended function can lead to wasting investment resources in test overhead which do not even stress the function of the intended usage. When the design for test engineer examines the usage of the circuit, then significant hardware resources can be realized; we pay less and get an even better quality test. One example of this concept is the testing of embedded trace arrays. First of all, one familiar with the problems of testing embedded arrays on VLSI chips understands the benefits but associated costs of array "built-in" self testing, ABIST. The benefits are reduced tester-to-chip pin connections, decreased tester memory requirements, and decreased test time. The costs are increased on-chip area to implement the ABIST and design resources to implement and verify the ABIST. Secondly, one familiar with the use of trace arrays for logging signals on a VLSI chip at the on-chip clock frequency understands the intended operation of the trace arrays. The logic external to the one write-read ported trace array will initiate a singular or a burst of write operations followed by a dump of the array contents via sequential read operations. While ABIST minimally implements a "march" sequence, such as READ data at address, WRITE opposite data at address, READ opposite data at address, this READ/WRITE/READ sequence is not the functional operating sequence of the trace arrays. Trace arrays functionally use the following sequence: WRITE/WRITE/WRITE/.../READ/READ/READ. By implementing the ABIST for the trace arrays to execute the latter test sequence, the hardware real estate required is significantly reduced plus the test is exercising the actual function. Specifically, to implement ABIST, the logic design shares the address incrementer used by the functional "trace control" logic. It then adds a second incrementer of equal size to source the data. One control bit is required for the WRITE-READ control. Additional control bits may include complement address control, complement data control, ripple address control, pause test control, and test done control. One additional bit is required to hold a fail condition should un...