Browse Prior Art Database

LRC CHECK ACROSS PCI BRIDGE FUNCTION

IP.com Disclosure Number: IPCOM000014292D
Original Publication Date: 1999-Dec-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

GW BATCHELOR: AUTHOR [+2]

Abstract

On a PCI bus containing a PCI bridge and multiple hosts and storage devices, a method is described to check and preserve the LRC across the bridge function as the hosts reads and writes to/from the storage device. Hosts writing to a Device When one of the host adapters on the secondary PCI bus writes to a storage device on the same bus, data first passes through the PCI bridge to a cache located on the primary PCI bus, then from the cache back through the PCI bridge to the storage device. The entire data stream is protected by LRC which the host generates and sends at the end of the each data transfer. The data and the LRC are stored in the cache and eventually stored on the device. The host may or may not be able to send the entire data transfer to the device in one PCI bus transaction, depending on the size of the transfer and the activity of the secondary PCI bus. For large data transfers up to 4K bytes, the data may be broken up into smaller data packets with LRC calculated across each packet until the entire transfer is complete. As data passes through the bridge from the secondary PCI bus to the primary PCI bus, the bridge will calculate and accumulate the LRC for each data packet with LRC Generator B (see figure above). At the end of each secondary PCI bus transaction, the accumulated LRC is stored in the PCI bridge's SRAM memory in a location that is reserved for the host which initiated the data transfer. Each host has 64K locations in SRAM reserved for LRC storage, with each location containing the accumulated LRC for data transfers within a 4K address boundary. This technique allows each host multiple data transfers through the bridge without contaminating the LRC accumulation and checking provided for a particular data transfer, by the LRC accumulation and checking for other data transfers.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

LRC CHECK ACROSS PCI BRIDGE FUNCTION

On a PCI bus containing a PCI bridge and multiple hosts and storage devices, a method is described to check and preserve the LRC across the bridge function as the hosts reads and writes to/from the storage device.

Hosts writing to a Device

When one of the host adapters on the secondary PCI bus writes to a storage device on the same bus, data first passes through the PCI bridge to a cache located on the primary PCI bus, then from the cache back through the PCI bridge to the storage device. The entire data stream is protected by LRC which the host generates and sends at the end of the each data transfer. The data and the LRC are stored in the cache and eventually stored on the device.

The host may or may not be able to send the entire data transfer to the device in one PCI bus transaction, depending on the size of the transfer and the activity of the secondary PCI bus. For large data transfers up to 4K bytes, the data may be broken up into smaller data packets with LRC calculated across each packet until the entire transfer is complete. As data passes through the bridge from the secondary PCI bus to the primary PCI bus, the bridge will calculate and accumulate the LRC for each data packet with LRC Generator B (see figure above). At the end of each secondary PCI bus transaction, the accumulated LRC is stored in the PCI bridge's SRAM memory in a location that is reserved for the host which initiated the data transfer. Each host has 64K locations in SRAM reserved for LRC storage, with each location containing the accumulated LRC for data transfers within a 4K address boundary. This technique allows each host multiple data transfers through the bridge without contaminating the LRC accumulation and checking provided for a particular data transfer, by the LRC accumulation and checking for other data transfers.

As the data is fetched from the cache located on the primary PCI bus back through the bridge to the secondary PCI bus, LRC Generator "A" will calculate the LRC. This LRC value is also stored in the PCI bridge's SRAM in a location that is reserved for the host that initiated the transfer at the end of the secondary bus PCI transa...