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Reduce Chip heat dissipation and improve Failure Rate

IP.com Disclosure Number: IPCOM000014296D
Original Publication Date: 2001-Dec-16
Included in the Prior Art Database: 2003-Jun-19
Document File: 1 page(s) / 27K

Publishing Venue

IBM

Abstract

Chip Failure Rates depend largely on the operating temperature of the Chip. The heat generated and operating temperature depend on the rate at which the internal circuits are clocked. Product developers are generally struggling with conflicting performance, product failure rate and heat dissipation requirements. This invention reduces the operating temperature for a given performance requirement, and may allow higher performance for given failure rate and environmental requirements. Chips for a given product are clocked at a fixed rate to meet a peak performance requirement, whereas in practice the times when the chip will need to meet that peak requirement are few and relatively short. During the 'off-peak' times the clock speed of the chip could be reduced, thus lowering its average operating temperature and failure rate. Product internal firmware can monitor how busy is each chip, and reduce the clock speeds during times of low workload. This could apply to processor chips by monitoring time spent in the 'idle' loop or wait state, and for data handling chips by monitoring the rate at which data is being transferred. 1

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Reduce Chip heat dissipation and improve Failure Rate

Chip Failure Rates depend largely on the operating temperature of
the Chip. The heat generated and operating temperature depend on
the rate at which the internal circuits are clocked. Product
developers are generally struggling with conflicting performance,
product failure rate and heat dissipation requirements. This
invention reduces the operating temperature for a given
performance requirement, and may allow higher performance for
given failure rate and environmental requirements.

     Chips for a given product are clocked at a fixed rate to
meet a peak performance requirement, whereas in practice the
times when the chip will need to meet that peak requirement are
few and relatively short. During the 'off-peak' times the clock
speed of the chip could be reduced, thus lowering its average
operating temperature and failure rate. Product internal firmware
can monitor how busy is each chip, and reduce the clock speeds
during times of low workload. This could apply to processor chips
by monitoring time spent in the 'idle' loop or wait state, and
for data handling chips by monitoring the rate at which data is
being transferred.

1