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Generation of N pulses with accurate timing windows

IP.com Disclosure Number: IPCOM000014312D
Original Publication Date: 2000-Dec-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 4 page(s) / 68K

Publishing Venue

IBM

Abstract

The increasing operating frequency of electronic sub assemblies and Very Large Scale Integration (VLSI) modules over several hundred of megahertz leads to work with signal pulse widths in the range of the nanosecond. At such speed, the rising and falling transitions of the pulses must be defined with a high accuracy. A current requirement is to precisely define signal transition with a dispersion of 100ps around nominal values. The location of transitions with respect to a reference signal is not the only specification. Some signals must also be defined with higher accuracy with respect to the others signals. An other kind of requirement is that two or more signals must overlay, that is to say one signal must rise before the other and fall after the other, providing a kind of timing aperture . In this case, the delay difference between signals could be as low as 100ps nominal value with a maximum allowed dispersion of 20ps.

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Generation of N pulses with accurate timing windows

The increasing operating frequency of electronic sub assemblies and Very Large Scale Integration (VLSI) modules over several hundred of megahertz leads to work with signal pulse widths in the range of the nanosecond. At such speed, the rising and falling transitions of the pulses must be defined with a high accuracy. A current requirement is to precisely define signal transition with a dispersion of 100ps around nominal values. The location of transitions with respect to a reference signal is not the only specification. Some signals must also be defined with higher accuracy with respect to the others signals. An other kind of requirement is that two or more signals must overlay, that is to say one signal must rise before the other and fall after the other, providing a kind of timing aperture . In this case, the delay difference between signals could be as low as 100ps nominal value with a maximum allowed dispersion of 20ps.

PRIOR ART :

    A well known technique to produce calibrated delays is to use a printed circuit board (PCB) delay line. The technique is illustrated by an example where the requirement is to provide cyclic pulses specified versus a timing reference (supposed to be 0ns) at transitions located between -.2ns and +1.2ns as shown on figure 1. Figure 2 shows an example of implementation on a real PCB design. The figure has been intentionally drawn to scale in order to highlight the size of the different components. The first component is Phase Lock Loop (PLL) device having at least two output drivers DA and DR . Output driver DR is fed back to the PLL input through a trace of length L,so that the PLL , when synchronised , has its output drivers rising transitions switching

before the reference signal rising transition. The PLL real size is typically in the range of 10mm. The second component includes a piece of logic . It can also be the module where the calibrated pulses are used , so that all connections are of negligible delay, since internal to a VLSI module. The user module is also in the range of 10mm. The consequence of small size components is that the distance between two adjacent signal leads or pins is in the range of 1mm, very small compared to the signal trace length. The PCB traces are drawn on figure 2 with thick lines. They are defined by their characteristic impedance Z0 and the signal speed V. Speed is a function of the relative permitivity epsilon r, given by :
V = C / epsilon r**1/2

C : velocity of light. Typically , epsilon r is in the range of 4 and the signal speed is around 7ps per mm or 142 mm per ns. Figure 2 is the physical implementation of an example requiring a pulse defined at a time negative versus the reference signal. La1 is the trace length (as short as possible) between the two components while Lr is a trace with extra length intentionally drawn to

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meet the -0.2ns timing requirements. In the case of a positive timing requ...