Browse Prior Art Database

ENHANCED PERIPHERAL COMPONENT INTERCONNECT BUS ERROR RECOVERY

IP.com Disclosure Number: IPCOM000014328D
Original Publication Date: 1999-Nov-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

CS GRAHAM: AUTHOR [+5]

Abstract

This invention provides for an explicit definition of the behavior of bridges and I/O adapters in the event of a peripheral component interconnect (PCI) bus error. The intent is to define the behavior in such a manner as to prevent hardware machine checks (even with some of the existing hardware implementations) and allow software to be able to recover from the following PCI bus errors: 1. Target Abort 2. Master Abort 3. Data Parity Error

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

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  ENHANCED PERIPHERAL COMPONENT INTERCONNECT BUS ERROR RECOVERY

This invention provides for an explicit definition of the behavior of bridges and I/O adapters in the event of a peripheral component interconnect (PCI) bus error. The intent is to define the behavior in such a manner as to prevent hardware machine checks (even with some of the existing hardware implementations) and allow software to be able to recover from the following PCI bus errors:

1. Target Abort
2. Master Abort
3. Data Parity Error
4. Address Parity Error

In order to perform the recovery, the state of the various bridges and I/O adapters must be known, as well as information must be available to the software to determine which bridges and I/O adapters have been involved. This invention defines two new functions - one that is applicable only to PCI bridges, and the other that is applicable to PCI bridges and I/O adapters. The first function that is only applicable to PCI bridges is labeled Freeze Mode. This mode has been introduced to define the behavior of a bridge in the event of any type of error taken during a posted-write or delayed transaction. The second function that is applicable to both PCI bridges and I/O adapters is the systems error record and retry (SERR) Disabled Interrupt. In many of the current PCI bridge implementations, SERR is either directly connected or explicitly forces a hardware machine check (Note that this facility has different names based on the platform, but the facility exists on all platforms and has similar consequences). In the event that a device that follows this invention is attached to the aforementioned bridge, the software can disable SERR following the PCI architecture, but still get the error reported via an external interrupt to the processor complex. In this manner, the software can proceed with error recovery, instead of a hardware machine check.

The figure illustrates a conventional computer system comprised of a Processor Complex [100] and a PCI backplane
[200]. The processor complex having a central processing unit (CPU) [110] and memory [120] interconnected by a processor memory bus [130]. The PCI backplane [200] having a PCI host bridge [210], I/0 device adapters [250], and PCI to PCI Bridge

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[230], interconnected by a PCI primary bus [220]. The PCI backplane [200] also having I/0 device adapters [250] and PCI to PCI Bridge [230] interconnected by a P...