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MAPPING LARGE PCI MEMORY WINDOWS ON A SECONDARY BUS TO SMALLER WINDOWS ON A PRIMARY BUS

IP.com Disclosure Number: IPCOM000014339D
Original Publication Date: 1999-Dec-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

CE JONES: AUTHOR [+3]

Abstract

MAPPING LARGE PCI MEMORY WINDOWS ON A SECONDARY BUS TO SMALLER WINDOWS ON A PRIMARY BUS

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This is the abbreviated version, containing approximately 51% of the total text.

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MAPPING LARGE PCI MEMORY WINDOWS ON A SECONDARY BUS TO

SMALLER WINDOWS ON A PRIMARY BUS

On a 32 bit PCI Bus, the addressing is architected for a maximum of 4 GB's of address space. This address space is shwred among all adapters within the system containing the PCI Bus. this addressing space can be inadequate in cases where the adapters require a large amount of address space. this is compounded when secondary PCI buses are used to extend the number of adapters tha can be attached to the system. In this case, you quickly exhaust the 4 GB's of allowed address space. This article will describe a means of expanding the PCI Bus address space by providing a mapping function between primary and secondary PCI buses.

In figure 1, a PCI Bus system is shown containing primary and secondary buses which require more than the allowed 4 GB's of addressing. PPCI-1 is the first primary PCI Bus, PPCI-2 is the second primary PCI Bus, and PPCI-3 is the third primary PCI Bus. Each of these primary PCI Buses have 3 slots for adapters. The secondary PCI Buses are designated SPCI-1, SPCI-2, and SPCI-3; they each have 4 PCI slots for adapters. The primary PCI buses each contain 3 PCI adapter cards in addition to the connection to their respective secondary PCI Buses via a custom PCI-PCI Bridge. Each of the secondary PCI Buses contain 4 PCI adapters. Each of the PCI adapters on the 3 secondary PCI Buses, requires 256 MB's of address space as do each of the adapters on the primary PCI Bus. This requires a total of greater than 4 GB's of address space. The Host processor complex has a total of 1 GB of address space requirements, which leaves each of the Host PCI Bridges with 1 GB of address space. With each of the 3 adapters needing 256 MB of address space, this leaves only 256 MB total for each of the secondary PCI Buses. However, they need 1 GB of total address space in addition to the 256 MB's needed by the PCI-PCI Bridge. To address each of the adapters on the secondary PCI Buses, their addresses must be mapped within the 256 MB's allotted to each of the PCI-PCI Bridges. This can be done in various ways, of which two methods will be presented here.

In the cases where the entire 256 MB's must be addressed, the adapters address space can be mapped to the entire 256 MB's by use of a slot enable function contained in the custom PCI-PCI bridge. This method of access could be used to send very large chunks of data to the adapters in a round robin fashion, by enabling the mapping of their address space one at a time. The slot enable function is controlled by a PCI configuration (Slot Control) register contained in the custom PCI-PCI Bridge. The other method, which allows simultaneous access to all adapters, maps just a portion of their address space at any given time. This allows essentially a method of paging into portions of the address space as needed. This method is useful when the adapter has portions of its address space that do not need to be accessed a...