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CIRCUIT TOPOLOGY TO MEASURE MR READ HEAD RESISTANCE AND CALIBRATE MR READ HEAD BIAS CURRENT

IP.com Disclosure Number: IPCOM000014344D
Original Publication Date: 2000-Aug-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Abstract

The below described circuit topology will allow the measurement of the MR read head resistance and also the calibration of the MR read head bias current. The measurement of the read head bias resistance is important to make sure that the maximum power dissipation of the head is not exceeded The calibration of the bias current is important to allow operating closer to the maximum power dissipation by reducing the tolerance on the programmed bias current. Shown below is the block diagram of the circuit topology used for measuring the MR read head resistance and calibrating the head bias current. The main blocks in the diagram above and their purpose are: 7 bit current DAC for setting the current going to the on bias generator

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  CIRCUIT TOPOLOGY TO MEASURE MR READ HEAD RESISTANCE AND CALIBRATE MR READ HEAD BIAS CURRENT

   The below described circuit topology will allow the measurement of the MR read
head resistance and also the calibration of the MR read head bias current. The
measurement of the read head bias resistance is important to make sure that the
maximum power dissipation of the head is not exceeded The calibration of the bias
current is important to allow operating closer to the maximum power dissipation
by reducing the tolerance on the programmed bias current.

Shown below is the block diagram of the circuit topology used for measuring the
MR read head resistance and calibrating the head bias current.

The main blocks in the diagram above and their purpose are:

7 bit current DAC for setting the current going to the on bias generator

which is biasing the selected head or the calibration resistor.
On switch blocks are large FET devices used to "steer" the biasing current

to a selected head or the calibration resistor.
4 to 1 analog MUX used to connect one of the inputs of the comparator to

one of the MR read heads or the calibration resistor.
Rail to rail comparator used to compare a reference voltage with the

voltage generated at the MR read head bias pins (1, 38, and 35) or the ICAL
calibration resistor pin (9).

Voltage divider used to generate 15 different reference voltages from an


1.


2.


3.


4.


5.

input reference voltage generated off chip.

For normal operation, MR read heads can be attache...