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Method to Improve Performance of Split-read Transactions

IP.com Disclosure Number: IPCOM000014358D
Original Publication Date: 2000-Oct-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Abstract

Disclosed is a way to improve performance in subsystems that use split-read type transactions on their interconnect buses, particularly pertaining to I/O subsystems. A split-read protocol is one where the read transaction (split-request) is requested by the master, the master gets off the bus, and then when the target is ready with the data, it becomes the master and sends the split-response data back to the initial requester. In a system where the interconnect protocols between components allow for split-read transactions, there is the problem of how to control the size of the request relative to the size of the available buffers in the components that must handle the split-response data. In addition, if the component is servicing multiple masters, it is necessary to balance the requests from the multiple requesters so that large requests don't prevent the servicing of other requests in a timely manner. That is, control of the latency in servicing the requests is important. An example of an interconnect which uses a split-read type transaction is the PCI-X I/O bus protocol. In the current state of the art, the way that this is solved is by limiting the maximum size of the request by the master. This is generally accomplished by having a programmable register in a requesting device that can be set by hardware-aware software. Through some platform-specific algorithm, the hardware-aware software then sets up these registers when the device comes on-line initially and generally doesn't change those after that (that is, they are static for the device from the time it is powered-up to the time it is powered down). This method is inefficient because it: (1) requires hardware-aware code, (2) does not allow for dynamic conditions like buses going from lightly loaded to heavily loaded and back to lightly loaded, etc., and (3) requires recalculation and reprogramming of all devices on the bus when a hot plug operation inserts another device on the bus. The following method solves this problem but does not have the three limitations of the current state of the art, as mentioned above. This method assumes that the split transaction protocol allows for the target to break up a large transaction such that the response is a series of responses that are smaller than the request. For example, the PCI-X I/O bus protocol allows this.

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Method to Improve Performance of Split-read Transactions

Disclosed is a way to improve performance in subsystems that use split-read type transactions on their interconnect buses, particularly pertaining to I/O subsystems.

A split-read protocol is one where the read transaction (split-request) is requested by the master, the master gets off the bus, and then when the target is ready with the data, it becomes the master and sends the split-response data back to the initial requester. In a system where the interconnect protocols between components allow for split-read transactions, there is the problem of how to control the size of the request relative to the size of the available buffers in the components that must handle the split-response data. In addition, if the component is servicing multiple masters, it is necessary to balance the requests from the multiple requesters so that large requests don't prevent the servicing of other requests in a timely manner. That is, control of the latency in servicing the requests is important. An example of an interconnect which uses a split-read type transaction is the PCI-X I/O bus protocol.

In the current state of the art, the way that this is solved is by limiting the maximum size of the request by the master. This is generally accomplished by having a programmable register in a requesting device that can be set by hardware-aware software. Through some platform-specific algorithm, the hardware-aware software then sets up these registers when the device comes on-line initially and generally doesn't change those after that (that is, they are static for the device from the time it is powered-up to the time it is powered down). This method is inefficient because it: (1) requires hardware-aware code, (2) does not allow for dynamic conditions like buses going from lightly loaded to heavily loaded and back to lightly loaded, etc., and (3) requires recalculation and reprogramming of all devices on the bus when a hot plug operation inserts another device on the bus.

The following method solves this problem but does not have the three limitations of the current state of the art, as mentioned above. This method assumes that the split transaction protocol allows for the target to break up a large transaction such that the response is a series of responses that are smaller than the request. For example, the PCI-X I/O bus protocol allows this.

The solution is to have the component accept only a few split-read requests from any given requester when a request that is larger than some fraction of the available buffer space is received. If multiple requests are queued which are larger than some fraction of the available response buffer space, then each request is broken up into multiple smaller requests within the component and these multiple requests from one requester are interleaved with the requests from other requesters. If there is only one devi...