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A Novel High Speed CMOS Signal Transition Detector Circuit

IP.com Disclosure Number: IPCOM000014372D
Original Publication Date: 2001-Apr-16
Included in the Prior Art Database: 2003-Jun-19
Document File: 5 page(s) / 89K

Publishing Venue

IBM

Abstract

Disclosed is a circuit that functions as a signal transition detector and which can operate at high speed, it is capable of detecting signal transitions at a data rate of 2 Gbit/s when implemented in a 0.18um CMOS process. The complete circuit uses an input comparator with offset to detect whether the input signal has moved a known level away from its quiescent state. If transitions are occurring then the output of the comparator will be switching and the circuit which is the subject of this disclosure provides a convenient means of detecting and storing this information. The circuit is claimed to be novel and offers the following advantages:

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A Novel High Speed CMOS Signal Transition Detector Circuit

Disclosed is a circuit that functions as a signal transition detector and which can operate at high speed, it is capable of detecting signal transitions at a data rate of 2 Gbit/s when implemented in a 0.18um CMOS process. The complete circuit uses an input comparator with offset to detect whether the input signal has moved a known level away from its quiescent state. If transitions are occurring then the output of the comparator will be switching and the circuit which is the subject of this disclosure provides a convenient means of detecting and storing this information. The circuit is claimed to be novel and offers the following advantages:

  Low component count High operating frequency Convenient implementation using standard CMOS process technologies Circuit Description

    A stream of input transitions which have an appropriate amplitude due, for example, to a comparator preprocessing an input signal, are supplied to the circuit shown in Figure 1. The PFET ( P1 ) and NFET (N1) form a charge pump which will inject charge into C1 during transitions of the input signal. However when the input is in either the high or low state, either P1 or N1 will be turned off and no charge will flow through P1 and N1 apart from leakage current. Consequently the capacitor C1 will only charge to the threshold of the sensing comparator if there is a sufficient frequency of input transitions such that the charge injected into the capacitor by P1 and N1 is greater than the charge removed by the current source Idis.

    The basis of this disclosure is the use of the P1 and N1 circuit configuration as a charge pump operating only during transitions of the signal on their gate terminals. The magnitude of the current injected into the capacitor is predominantly dependant upon the FET parameters and can be controlled through the geometric design of these devices. The simplicity of this circuit enables it to operate at high speed and it can be easily integrated onto a chip together with the capacitor C1.

    The use of a charge pump introduces a time constant into the transition detector such that any subsequent circuits which monitor the output of the detector can operate at much slower speeds then the detector itself. It also prevents occasional random events, such as noise glitches, from being misinterpreted as valid signal transitions. This can be an advantage for these types of circuit by preventing spurious outputs of the detector during events such as system power-up.

    The threshold comparator simply detects when the voltage across the charge pump capacitor has exceeded a reference threshold and sets the output. This threshold level together with the capacitor and operating currents ( P1/N1 switching current and Idis ) sets the time constant for operation of the detector. The threshold comparator can contain hysteresis to ensure fast switching of the output in applications where the capacitor voltage mo...