Browse Prior Art Database

Level Sense Power On Reset Circuit

IP.com Disclosure Number: IPCOM000014397D
Original Publication Date: 2000-May-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 4 page(s) / 179K

Publishing Venue

IBM

Abstract

Disclosed is a method to provide power on reset pulse of enough height even if rise speed of power supply is considerable slow. This circuit is implemented inside LSI chip and it resets internal memory devices such as latches, flip flops and registers and confirms initial state of those devices.

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Level Sense Power On Reset Circuit

    Disclosed is a method to provide power on reset pulse of enough height even if rise speed of
power supply is considerable slow. This circuit is implemented inside LSI chip and it resets internal
memory devices such as latches, flip flops and registers and confirms initial state of those devices.

As technology proceed on and on, power supply voltage is lowered for low power application. This
makes it difficult to generate power on reset pulse with enough height. According to this method, the
pulse height of the power on reset pulse is high enough by voltage sense mechanism with diodes.

Figure 1 shows conventional power on reset circuit. This circuit has large capacitance C and
resistance R to generate long charge up time. When the power is on, the capacitance C begins to be
charged with path P through the resistance R. This charge up time should be long enough compared with
the rise time of power supply in order to generate power on reset pulse of enough height. However the
values of C and R are limited due to on-chip implementation. The maximum time constant CR which can
be implemented on chip is about 1 msec even if ON resistance of MOSFET and poly-diffusion capacitance
are used to implement R and C for area saving. The power supply rise time ranges from hundreds of
micro-seconds to scores of milli-seconds. This causes low power on reset pulse and reset fail problem
because the voltage of the power supply has not reached a enough voltage for resetting internal
devices. Figure 2 shows the simulation result for the circuit. The height of the pulse is low when
process is worst and rise speed of power supply is slow.

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1.651.65 1.651.65 1.651.65

1.16

0.93

1.8

1.6

Vph (V)

1.4

Worst Nominal Best

1.2

1

0.8

1E+3 1E+4 1E+5 1E+6 1E+7 1E+8

Trise (nsec)

Fig. 2 C onventional P O R C ircuit S imulation R esult

Figure 3 shows proposed power on reset circuit. In this circuit, charge path P1 has two diodes D1 and
D2. The charge up does not start until power supply voltage is beyond the level at which these 2
diodes are on. And in this circuit, charge up boost path P2 is used to accelerate charge up once
charge capacitance voltage reaches a certain level. This mechanism is implemented with inverter I2
and transistor T3. Further, feedback transistor T5 is place...