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Browse Prior Art Database

Improved Algorithm for calculating the negative voltage offset for reading by a positive A/D.

IP.com Disclosure Number: IPCOM000014463D
Original Publication Date: 2000-Jan-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 6 page(s) / 108K

Publishing Venue

IBM

Abstract

The Nefinity Servers use a divider similar to the one shown in Figure 1. to translate the -5v to a positive voltage so that it can be read by a 0-5v Analog to Digital Converter (A/D). The current calculation used to calculate the -5v voltage is inaccurate. This invention uses a unique approach that produces a much more accurate result. This Invention Disclosure describes a method that uses a sensitivity analysis of the circuit as the basis for the algorithm, resulting in a simpler more accurate equation that can be readily executed by an embedded controller. Referring to the Figure, the output Voltage (V0) can be obtained by Thevinizing the Voltage divider yielding 1.)

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  Improved Algorithm for calculating the negative voltage offset for reading by a positive A/D.

  The Nefinity Servers use a divider similar to the one shown in Figure 1. to translate the -5v to a positive voltage so that it can be read by a 0-5v Analog to Digital Converter (A/D). The current calculation used to calculate the -5v voltage is inaccurate. This invention uses a unique approach that produces a much more accurate result.

This Invention Disclosure describes a method that uses a sensitivity analysis of the circuit as the basis for the algorithm, resulting in a simpler more accurate equation that can be readily executed by an embedded controller.

Referring to the Figure, the output Voltage (V0) can be obtained by Thevinizing the Voltage divider yielding

1.)

2R+1RRV0 =4(V2R1+V1R2)

R1R2 (1R+3R)(2R+1R+(2R1RR=R1+R2 +R3+R44(V2R1+V1R2)R4) = R4(V2R1+V1R2)3

Equations 2-6 is a sensitivity analysis of the Voltage Divider components. The " ¶ " is the symbol for the Sensitivity Algebra operator not integration.

1

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2). From 1 R(2R)+4R+3R+2R(1RRqV0 = ¶q4(V2R1+V1R2)3+R4) = ¶qR4 + ¶qV2R1+V1R2 - ¶

3). But, ¶qV2R1+V1R2 = V2R1

RVV2R1+V1R2 (q2 +q1)+ V1R2

RVV2R1+V1R2 (q1 +q2)

4).And,

q

R 1R 2+ R1 R 3+R 1 R 4+R 2 R 3+R 2 R 4

= R 1R 2

R(R 1 R 2 + R 1R 3 + R 1R 4 + R 2R 3 + R 2R 4 q 1 + qR 2 )+

            R 1R 3 R(R 1R 2 + R 1R 3 + R 1R 4 + R 2R 3 + R 2R 4 q 1 + qR 3 )+

            R 1R 4 RR 1R 2 + R 1R 3 + R 1R 4 + R 2R 3 + R 2R 4 ( q 1 + qR 4 )+

            R 2R 3 (R 1R 2 + R 1R 3 + R 1R 4 + R 2R 3 + R 2R 4 qR 2 + qR 3 )+

            R 2R 4 R(R 1R 2 + R 1R 3 + R 1R 4 + R 2R 3 + R 2 R 4 q 2 + qR 4 )

Collecting terms from 2), 3), and 4) yields

5).

q

V 0

=( V 2 R 1

R-V 2 R 1 + V 1 R 2 1 R 2 + R 1 R 3 + R 1 R 4

R)R 1 R 2 + R 1 R 3 + R 1 R 4 + R 2 R 3 + R 2 R 4 q 1 +

+( V 1 R 2

R-V 2 R 1 + V 1 R 2 1 R 2 + R 2 R 3 + R 2 R 4

R)R 1 R 2 + R 1 R 3 + R 1 R 4 + R 2 R 3 + R 2 R 4 q 2 +

- R 1 R 3 + R 2 R 3

R 1 R 2 + R 1 R 3 + R 1 R 4 + R 2 R 3 + R 2 R 4 qR 3 +

+( 1 - R 1 R 4 + R 2 R 4

R)R 1 R 2 + R 1 R 3 + R 1 R 4 + R 2 R 3 + R 2 R 4 q 4 +

+ V 2 R 1

VVV 2 R 1 + V 1 R 2 q 2 + 1 R 2

VV 2 R 1 + V 1 R 2 q 1

6). Assuming R1 = 10K , R2 = 56K , R3 = 470 , R4 = 130K , V1 = 5V, V2 =-5V then

R1V0 =-.417, ¶R2V0 = .360, ¶R3V0 =-.00315, ¶R4V0 = .060, ¶V1V0 = 1.217, ¶V2V0 =-.217

2

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What we want to know is for a 1 bit change in C0 (the CV count of V0) how must did V1 have to change or 20 , tbim17.2 but V0 = C0bits %v => V0 = 17.2mvC0

Assuming that the % is small and that the cross R sensitivities are negligible (i.e. Vc1 = ¶VcR2 = 0). , then by definition
0VVV 7). %V0 ¡ ¶V20 %V2 but, %V0 = 0 and %V2 =V2V2 =>

8). V2 VV0 =2

V+1R2V3R(2R)+4R+3R+2R(1R)2R1V+1R2V(4RV=V0V2V02+R4) % V2R11R2 =>

but

9).

V0 C0 =

Combining 8) & 9) yields

10).

RV2 = C0 %4(V2R1+V1R2)

RC0n(R1(R2+R3+r4)+R2(R3+R4)) %1(R2+R3+R4)+R2(R3+R4)

CR1R4 =0(V2R1+V1R2)

C0nR1

    R4(V2R1+V1R2) R1(R2+R3+r4)+R2(R3+R...