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Method and Apparatus to Attach Devices Implementing a Motorola MPC860 External Bus Interface to the IBM CoreConnect Processor Local Bus

IP.com Disclosure Number: IPCOM000014467D
Original Publication Date: 2000-Nov-01
Included in the Prior Art Database: 2003-Jun-19
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Abstract

Method and Apparatus to Attach Devices Implementing a Motorola MPC860 External Bus Interface to the IBM CoreConnect Processor Local Bus

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This is the abbreviated version, containing approximately 52% of the total text.

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Method and Apparatus to Attach Devices Implementing a Motorola MPC860

External Bus Interface to the IBM CoreConnect Processor Local Bus

The disclosed device is a bridge between the *IBM CoreConnect PLB bus and an on-chip implementation of the **Motorola MPC860 bus. The disclosed device enables reuse of existing Motorola MPC860 bus devices with minimal modification. This bus bridge provides savings in engineering costs.

The MPC860 bus to which the disclosed bridge is attached is not a true external bus. It is an on chip implementation of the MPC860 external bus. Because this bus is implemented on chip, and is intended to be implemented in an IBM *BlueLogic technology, none of the MPC860 bus signals may enter a high impedance state. For this reason, when MPC860 bus control lines are not in use, they must always be driven to their inactive state. Other than this, the on chip MPC860 bus is logically consistent with the Motorola MPC860 external processor bus. For simplicity, this document will refer to the on chip MPC860 bus as the "EMBUS", and will refer to the disclosed device as the "PLB to EMBUS bridge" or simply the "bridge."

Either the bridge or attached device may function as the EMBUS master. Each device as a master will request ownership of the bus, and the bridge is responsible for arbitrating and granting ownership to the requesting EMBUS master in a fair manner. The bridge functions as an EMBUS slave when the attached device is the EMBUS master, the same device functions as the EMBUS slave when the bridge is the EMBUS master.

The bridge also functions as both a master and a slave on the PLB and is compliant with the "Processor Local Bus Architecture Specification, Version 3.2." There are two primary transaction flow patterns through the bridge. A transaction may flow through the bridge from PLB slave to EMBUS master, or it may flow from EMBUS slave to PLB master. Transaction data may flow in either direction between these bridge master/slave pairs. Write data always flows within the bridge from slave to master, and read data flows from master to slave. Bridge slaves are responsible for decoding a transaction from an initiating master on the primary bus and for forwarding the transaction to the bridge master unit on the remote bus. Bridge slaves are also responsible for completion of the transaction on the primary bus. Bridge masters receive transaction requests from bridge slaves and are responsible for requesting the remote bus, completing the transaction on the remote bus, and acknowledging the bridge slave.

The bridge EMBUS master is intended to perform byte, word or halfword aligned read and write transactions targeted at EMBUS slaves. For this reason, the bridge PLB slave that initiates transactions to the bridge EMBUS master is designed to be only a 32 bit slave. The PLB slave will not claim any PLB transaction that cannot be transferred to the EMBUS in a single transaction. Any PLB master request in the bridge slave'...